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14th VLSI Design And Test Symposium
VDAT2010

July 7-9, 2010
Chitkara University Campus, Himachal Pradesh, India
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Softcopy proceedings: Symposium
Softcopy proceedings: Tutorials

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Tutorials | Analog | Power Management | Low-power | CAD
NoC | Biomedical | Interconnect
Invited talks | Architecture | Devices | Test & Verification | Research Scholar Forum

Tutorials

Fundamentals of SoC Power Management Architecture Design and Verification
Bhanu Kapoor (Mimasic); Prapanna Tiwari (Synopsys); John Goodenough (ARM Embedded Technologies); Amit Kumar (Sirf/CSR); and Milind Padhye (Freescale)

Session 1A-1 Tutorial - T1-A Half day Tutorial

VLSI and System Design for Solar PV Energy Management - Why, What and How
Nagavolu Murty; Mukesh Nair; Jayalakshmi P; and Mahadev Cholachagudda (NXP Semiconductors)

Session 1A-2 Tutorial - T1-B Half day Tutorial

Network-on-Chip: The Next Generation of Multi-Processor System-on-Chip
Santanu Chattopadhyay; and Santanu Kundu (IIT Kharagpur)

Session 1B-1 Tutorial - T2-A Half day Tutorial

Video Codecs for Embedded Multimedia Systems
Milind Phadtare (NXP Semiconductors)

Session 1B-2 Tutorial - T2-B Half day Tutorial

An Overview of Modern-day VLSI Design and Test
C.P. Ravikumar (Texas Instruments, India)

Session 1C Tutorial - T3

Technical papers

Analog

CMOS Transconductance Element for Low-Frequency Applications
Venkatesh Acharya (Texas Instruments)

Session 2A-2 Analog 1 Regular Paper

Design of a 10bit, 5 MS/s Pipelined ADC for CMOS Image Sensor
Kanhu Charan Behera; M. Santosh; and S.C.Bose (Central Electronics Engineering Research Institute, Pilani)

Session 2A-2 Analog 1 Regular Paper

Design of 6-bit Folding & Interpolating ADC
Shruti Oza (Kalol Institute of Technology); and Niranjan Devashrayee (Nirma University of Science & Technology)

Session 2A-2 Analog 1 Regular Paper

A Short Tutorial on Analog Layout Challenges in Deep Submicron Technologies
Vishwanath Hanchinal; and Vijay Mundlapudi (NXP Semiconductors India)

Session 2A-3 Analog 2 Short Tutorial

A Sensitivity Analysis Based Approach to Statistical Parameter Estimation of Analog Circuits
Arnab Khawas (IIT, Kharagpur); and Amitava Banerjee (National Semiconductor Corp, India)

Session 2A-3 Analog 2 Regular Paper

Asynchronous ADC Using Novel Asynchronous Subranging Scheme
Anita Deshmukh; Ravi Patil; Raghvendra Deshmukh; and Rajendra Patrikar (VNIT, Nagpur)

Session 2A-3 Analog 2 Regular Paper

Power Management

A Novel Curvature Compensation Technique for voltage reference circuit
K. Praveen Kumar Reddy; and Rajendra M. Patrikar (VNIT, Nagpur)

Session 2A-4 Power Management 1 Regular Paper

A Tutorial on Battery Simulation - Matching Power Source to Electronic System
Vishwani Agrawal; and Manish Kulkarni (Auburn University)

Session 2A-4 Power Management 1 Short Tutorial

Low-power

Robust and Self-Adaptive Power Reduction Techniques for FIFO Buffers
Salil Gadgil; Senthilkannan C; and Anuja Bagdi (Texas Instruments India Pvt Ltd)

Session 2B-2 Low-power 1 Regular Paper

A Technology Specific Approach to Reduce Leakage
Sambhu Nath Pradhan (KIIT University); and Santanu Chattopadhyay (IIT Kharagpur)

Session 2B-2 Low-power 1 Regular Paper

Novel Low Power Multipliers using Bypassing Schemes
P Saravanan; and S Brinda (PSG College of Technology)

Session 2B-2 Low-power 1 Regular Paper

Design of Static Latch-based Comparators using Power Constrained Optimization
Purushothaman A; and Chetan D. Parikh (DAIICT)

Session 2B-4 Low-power 2 Short Paper

Low Power Decoupling Circuit
Dharmaray Nedalgi (NXP Semiconductors)

Session 2B-4 Low-power 2 Short Paper

Low Power Means to High-Speed Current Switching
K.R. Srinidhi Koushik; and Lavanya Nirikhi (Sasken Communication Tech. Ltd.)

Session 2B-4 Low-power 2 Short Paper

CAD

Fast CMOS Circuit design: High Speed Library Design
Akhtar W. Alam (ARM Embedded Technologies)

Session 2B-3 CAD Short Tutorial

Implementation of Fault Tolerant Feedforward Neural Networks in VLSI Hardware
N. Mohankumar; M. Nirmala Devi; and Jayalakshmi P. Nair (Amrita Vishwa Vidyapeetham)

Session 2B-3 CAD Regular Paper

Static Timing Analysis of IO Interfaces for Large SoCs
Rahul Vishal; Sagar Mallik; and Vinita Alphonsus (NXP Semiconductors India Pvt. Ltd)

Session 2B-3 CAD Short Tutorial 1hr

NoC

Handling Multiple Hotspots in Wormhole NoCs
Hemangee Kapoor; Shirshendu Das; and B.V.Balakrishna (IIT Guwahati)

Session 2C-2 NoC Short Paper

Minimal Path Fault Tolerant Routing in 2-D Mesh NoC
Navaneeth Rameshan; Manoj Gaur; Mushtaq Ahmed; and Vijay Laxmi (MNIT, Jaipur)

Session 2C-2 NoC Regular Paper

Biomedical

FPGA based Fuzzy Neural Signal Processing System for QRS Complex Detection in Noisy ECG Signals
Shubhajit Roy Chowdhury (Jadavpur University)

Session 2C-3 Biomedical Regular Paper

A Novel Approach to Digital Filter Implementation for Hearing Aids
Subathra Devi N; and Raja Lakshmi K (PSG College of Technology)

Session 2C-3 Biomedical Regular Paper

New Techniques for Droplet Routing in Digital Microfluidic Biochips
Pranab Roy; Tuhina Samanta; Hafizur Rahaman (BESU, Shibpur); and Parthasarathi Dasgupta (IIM, Calcutta)

Session 2C-3 Biomedical Regular Paper

Comparative Analysis of Fertilization of Human Egg Using Morphological Operations and Parameters

Session 2C-3 Biomedical Regular Paper

Interconnect

A Closed Form Expression for Slew Metric for On-chip VLSI RC Interconnects using F-distribution Function
Rajib Kar; Abirjyoti Mondal; Vikas Maheshwari; Ashis K Mal; and Anup Kumar Bhattacharjee (NIT Durgapur)

Session 3A-2 Interconnect Short Paper

An Accurate delay Metric for Global On-chip VLSI RC Interconnects using First Three Circuit Moments
Rajib Kar; Vikas Maheshwari; M.Sunil Kumar Reddy; Vasundhara Agarwal; Ashis K Mal (NIT Durgapur); and Anup Kumar Bhattacharjee (NIT Durgapur)

Session 3A-2 Interconnect Regular Paper

Crosstalk Estimation in Coupled Interconnect lines using State Space Approach
Soorya Krishna; and M.S. Bhat (NITK, Surathkal)

Session 3A-2 Interconnect Short Paper

Analysis of Current Mode Drivers for VLSI Interconnect Systems
Sunil Jadav; Gargi Khanna; and Ashok Kumar (NIT, Hamirpur)

Session 3A-2 Interconnect Short Paper

Keynote and Invited Talks

Opportunity Unlimited Emerging Markets in India
Jaswinder S. Ahuja (Corporate VP and MD, Cadence Design Systems, India)

Session 2A-1 Keynote Keynote-1
Download Keynote-1 foils in PDF 11.67MB

Cloud Computing and its implication to EDA
Hasmukh Ranjan (VP Engineering Compute & Infrastructure Services, Synopsys, India)

Session 2A-1 Keynote Keynote-2

Harnessing Power of Multi-cores
Prof.Anshul Kumar (IIT Delhi)

Session 3A-1 Keynote Keynote-3

Design and Test of High-speed Chip-to-chip IO Interfaces to Improve TTM
Aninda K. Roy (Intel Corporation)

Session 2C-2 Invited Invited Talk

Architecture

Hybrid 16*16 Multiplier Based on Tree and Iterative Array concepts
Ayon Dey; Deepak Agarwal (Texas Instruments); and DV Poorniah (Bits-Pilani, Bangalore Center)

Session 3A-3 Architecture Short Paper

High Speed Low power Floating Point Multiplier Design based on CSD (Canonical Sign Digit)
Prabir Saha; A Banerjee; I Banerjee (Jadavpur University); and A Dandapat

Session 3A-3 Architecture Regular Paper

Semi-auto-visual Techniques to Capture Eight Indispensible Blood Parametres at PHC
Vikal Ingle (B.D. College of Engineering, Sevagram, Wardha); and Dr Pramod B.Patil (Jaidev College of Engineering, Nagpur)

Session 3A-3 Architecture Short Tutorial

Devices

Analytical Modeling for Estimation of Drain Current in Irradiated NanoScale Double Gate FinFET Device
Surendra S. Rathod; Ashok K. Saxena; and Sudeb Dasgupta (IIT Roorkee)

Session 3B-2 Devices Short Paper

Performance Evaluation of FinFET and Planar MOSFET Devices at Circuit Level for 45nm Technology
Sanjay B. Prajapati; Niranjan Devashrayee (Institute of Technology, Nirma University, Ahmedabad); Rajesh Thakker (Vishwakarma Govt. Engg. College, Chandkheda, Gujarat); Maryam Shojaei Baghini; and Mahesh B. Patil (IIT Bombay)

Session 3B-2 Devices Regular Paper

Fault Tolerant Design With Coupled Majority-Minority QCA Gate
Mamata Dalui (Haldia Institute of Technology); Bibhash Sen (NIT, Durgapur); and Biplab K. Sikdar (Bengal Engg and Science University)

Session 3B-2 Devices Regular Paper

Constant Bias Current Gain Variation Method for Weak and Strong Inversion MOSFETs
Anurag Zope; W.S. Khokle; Raghvendra Deshmukh; and Rajendra M. Patrikar (VNIT, Nagpur)

Session 3B-2 Devices Short Paper

Test & Verification

PLI Based Verification Setup for Fast System Level Verification
Anin George (Sasken Communication Tech Ltd)

Session 3C-3 Test & Verification Regular Paper

Reducing the Debugging Effort at FPGA Emulation
Naveen Tiwari (Samsung India Software Operations Pvt. Ltd)

Session 3C-3 Test & Verification Regular Paper

Signature Based Successive Reduction Diagnosis Flow for Embedded Read-Only Memories in a BIST Environment
Suraj Prakash (ST Microelectronics)

Session 3C-3 Test & Verification Regular Paper

Research Scholar Forum

CMOS-LTE Comparator and 2:1 Multiplexer in Flash ADC Design
Meghana Kulkarni (GIT, Belgaum, Karnataka, India); V. Sridhar (P.E.S. College of Engineering, Mandya); and G. Kulkarni (Gogte Institute of Technology, Belgaum, Karnataka)

Session 3B-3 Research Scholar Forum RSF

A FinFET based Robust Sense Amplifier for Process Variations
Vivek Harshey; Ashok K. Saxena; and Sanjeev Manhas (IIT Roorkee)

Session 3B-3 Research Scholar Forum RSF

Design of a Novel CNTFET-Based 1-Bit Full Adder in Deep Submicron Technology
Aminul Islam (BIT, Mesra, Ranchi); Sachin Pable; M.W. Akram; and Mohd. Hasan (AMU, Aligarh)

Session 3B-3 Research Scholar Forum RSF

Design of Robust Subthreshold Circuits
S.D. Pable (AMU, Aligarh); Aminul Islam (BIT, Mesra, Ranchi); M.W. Akram; and Mohd. Hasan (AMU, Aligarh)

Session 3B-3 Research Scholar Forum RSF

 

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