12th VLSI Design And Test Symposium

July 23-26, 2008
Wipro Campus, Electronics City, Bangalore
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Analog | Biomedical Applications | Digital Design | Interconnect | Low-power | Memory
RF Design | Technology | Testing | Timing | Verification | Invited talks


A CMOS Comparator Circuit Optimized for Power-Delay Product and Input-Output Isolation
Amit Kumar Gupta (Cadence Design Systems, Noida); and Chetan Parikh (DA-IICT Gandhinagar)
Session: 3A-4 Analog-2 Regular Paper Page: 10-17
High Speed CML Transmitter with On-chip PVT compensation for Improved Gain and Linearity Errors
Navin Kumar; Umesh Shukla; and Sankarareddy Kommareddi (IBM India Pvt Ltd)
Session: 3A-2 Analog-1 Regular Paper Page: 29-37
Macromodel based Fault Simulation of Opamp using Parameters Estimation
Kiran Kumar Garje; Srikanth Pam; Amitava Banerjee; Santosh Biswas; and Siddhartha Mukhopadhyay (IIT Kharagpur)
Session: 4A-2 Analog-4 Regular Paper Page: 38-48
Performance Comparison of CNFET and CMOS based Full Adders at the 32nm Technology Node
Tarun Agrawal; Anurag Sawhney; Abdul Kadir Kureshi; and Mohd. Hasan (Aligarh Muslim University)
Session: 3A-4 Analog-2 Regular Paper Page: 49-57
Ultra Wideband Variable Gain Amplifier Design for Software Defined Radio Applications
Neeraj Kumar; Parul Chopra; and Roy Paily (IIT Guwahati)
Session: 3A-2 Analog-1 Regular Paper Page: 58-65
Design of Low Power Low Pass Filter for ECG Application With Deep Submicron Technology
Amey M. Walke; Waman S. Khokle (VNIT, Nagpur); and Rajendra Patrikar (CRL, India)
Session: 3A-5 Analog-3 Short Paper Page: 74-82
Selecting an Optimum Bias Current for an Auxiliary Amplifier in Gain Boosting Amplifier for Power Optimization
Vinayak Pachkawade (VNIT, Nagpur); and Rajendra Patrikar (CRL, India)
Session: 3A-5 Analog-3 Short Paper Page: 83-90
Slew Rate Improvement Technique for High Frequency and Large Amplitude Signals
Benny Thomas; and Roy Paily (IIT Guwahati)
Session: 3A-5 Analog-3 Short Paper Page: 91-98

Biomedical Applications

Sensor Integration in an RFID Tag for Monitoring Biomedical Signals
Sandeep Reddy Munnangi; Roy Paily P.; Rakesh Singh Kshetrimaym; Genemala Haobijam; and Manikumar Kothamasu (IIT Guwahati)
Session: 2C-6 Biomedical Applications Poster Paper Page: 443

Digital Design

High Performance Elliptic Curve Crypto-processor for FPGA Platforms
Chester Rebeiro; and Debdeep Mukhopadhyay (Dept of CSE, IIT Madras)
Session: 3B-4 Digital Design-1 Regular Paper Page: 107-117
Mesh-of-Tree Based Network-on-Chip Architecture using Virtual Channel Based Router
Santanu Kundu; and Santanu Chattopadhyay (IIT Kharagpur)
Session: 3B-4 Digital Design-1 Regular Paper Page: 118-128
Design, Simulation and Testing of a High Performance 15-4 Compressor
Shubhajit Roy Chowdhury; Aniruddha Roy; Aritra Banerjee; and Hiranmay Saha (Jadavpur University)
Session: 3B-5 Digital Design-2 Short Paper Page: 147-154
Low Latency LSB First Bit-Parallel Systolic Multiplier over GF(2m)
Hafizur Rahaman; Prasenjit Ray; and Somsubhra Talapatra (BESUS)
Session: 3B-5 Digital Design-2 Short Paper Page: 163-172
High-Speed, High-Throughput Pipelined and Parallel Architecture for SPIHT algorithm
Anilkumar Nandi (BVB College of Engg. & Tech)
Session: 2B-6 Digital Design Poster Paper Page: 434
Novel Circuits for Two's Complement of a Binary Number
Rahul Badghare; Raghavendra Deshmukh (VLSI Design Labs, VNIT, Nagpur); and Rajendra Patrikar (CRL, India)
Session: 2B-6 Digital Design Poster Paper Page: 439
Optimization of High- Performance RF MEMS Capacitive Shunt Switch for Phase- Shifter Applications at Ku band
Avra Kundu (Jadavpur University); Sasanko Maji (Indian Association for the Cultivation of Sciences); Bhaskar Gupta; Samir Lahiri; and Hiranmay Saha (Jadavpur University)
Session: 3B-6 Digital Design-3 Poster Paper Page: 440


A Fast and Efficient Crosstalk Closure Methodology for Multi-million Gate SoCs
Chirag Gupta; Soujanna Sarkar (Texas Instuments India); and Saravanan Karunavel (Montalvo Systems)
Session: 3C-6 Interconnect Regular Paper Page: 337-346
Cross-talk Mitigation in Coupled VLSI Interconnects
Gargi Khanna; Preeti Sharma; Rajeevan Chandel (NIT Hamirpur HP); and Sankar Sarkar (FET, Mody Institute of Tech. & Sci., Rajasthan)
Session: 3C-6 Interconnect Embedded Tutorial Page: 364-374
A Framework for Dynamic Analysis of SoC Power Grids at Planning Stage
Jairam Sukumar (Texas Instruments); and Jayesh Jayarajan (Delhi College of Engineering)
Session: 3C-6 Interconnect Poster Paper Page: 421-422
Bus Synchroniser Technique used in Dynamic Frequency Scaling
Shalini Sharma (Freescale Semiconductors)
Session: 3C-6 Interconnect Poster Paper Page: 426


Dynamic Threshold PMOS Switch for Power Gating
Naushad Alam; Abdul Kadir Kureshi; and Mohd. Hasan (Aligarh Muslim University)
Session: 4C-2 Low power-1 Regular Paper Page: 173-180
A History based Technique for Low Power Bus Encoding
Santanu Chattopadhyay; and Srujan Reddy (IIT Kharagpur)
Session: 4C-2 Low power-1 Short Paper Page: 181-188
Input Assignment Technique for Low Power Circuit Testing
Subhadip Kundu; Kanchan Manna (IIT KGP); Tapas Kr. Maiti (College of Engg. & Management, Kolaghat); and Santanu Chattopadhyay (IIT Kharagpur)
Session: 4C-2 Low power-1 Short Paper Page: 189-196
Power Estimation of Different Arbitration Techniques for On-Chip Bus Based Reconfigurable Soc Platform
Srinviasan N; HemaChitra S; and Vanathi P.T. (PSG College of Technology)
Session: 4C-4 Low power-2 Short Paper Page: 197-204
Leakage-aware Synthesis of Multilevel Logic Circuits based on BDD Manipulation and Output Phase Selection
Saurabh Chaudhury (NIT Silchar); and Santanu Chattopadhyay (IIT Kharagpur)
Session: 4C-4 Low power-2 Poster Paper Page: 436-437
Low Power Discrete Time FIR Pulse Shaping Filter Design Algorithm using Linear Programming Technique
Shalini Sharma (Freescale Semiconductors)
Session: 4C-4 Low power-2 Poster Paper Page: 438
Performance Comparison of CNFET and CMOS based 8T SRAM Cell in Deep Submicron
Abdul Kadir Kureshi; Naushad Alam; and Mohd. Hasan (Aligarh Muslim University)
Session: 4C-4 Low power-2 Poster Paper Page: 441-442


600 MHz 18 Kb Ternary Content Addressable Memory
M Sultan M Siddiqui; and G S Visweswaran (IIT Delhi)
Session: 4A-4 Memory-1 Regular Paper Page: 205-211
Efficient Modeling of Memory Controllers in SystemC
Aravinda Thimmapuram; and Raghunath Gannamaraju (NXP Semiconductors)
Session: 4A-4 Memory-1 Embedded Tutorial Page: 212-216
New March Tests for Static and Dynamic Linked Faults in Random Access Memories
Shailender Reddy.K (IIT Bombay); Sanjay K. Thakur, and Rubin A. Parekhji (Texas Instruments India); and Arun N. Chandorkar (IIT Bombay)
Session: 4A-4 Memory-1 Regular Paper Page: 217-227
A SEU Tolerant Distributed CLB RAM for In-Circuit Reconfiguration
Karthik Kumar Srivatsa; Shyam Venkatesh; N. Rama Subramaniam (IIT Madras); Shoaib Mohammad (NIT Trichy); Noor Mahammad; and Veezhinathan Kamakoti (IIT Madras)
Session: 4A-4 Memory-1 Short Paper Page: 228-238

RF Design

A Pulse Width Modulated DC-DC Buck Converter using On-chip Inductor
Rohan Kesireddy; Jyothi Bhaskarr Amarnadh; Genemala Haobijam; and Roy Paily (IIT Guwahati)
Session: 2A-6 RF Design Poster Paper Page: 423
Design of an RF CMOS LNA using 0.25 Micron Technology
Pranjal Rastogi (Texas Instruments); Karthik Jayaraman (Analog/ RF Research group, Oregon State University, USA); and Rajnish Sharma (BITS, PILANI)
Session: 2A-6 RF Design Poster Paper Page: 429-430


Analytical Modeling and Simulation of Fixed-Fixed beam RF MEMS Resonator
Vaishali Mungurwadi (BVB College of Engg. & Tech.,); and Uday Wali (KLE College Belgaum)
Session: 4B-2 Technology-1 Regular Paper Page: 239-247
Metal Gate CMOS from the Device Variability Perspective
H. C. Srinivasaiah (EPCET); and Navakant Bhat (Indian Institute of Science)
Session: 4B-2 Technology-1 Regular Paper Page: 258-268


A Primal-Dual Solution to Minimal Test Generation Problem
Mohammad Shukoor and Vishwani Agrawal (Auburn University)
Session: 3C-4 Testing-2 Regular Paper Page: 269-279
Cellular Automata and LFSR Coupling for Pattern Generation: A Feasibility Study
Susmit Maity; Pushan Mitra; Prasenjit Ghosh; and Biplab Sikdar (Bengal Engg. And Science Univ.)
Session: 3C-5 Testing-3 Regular Paper Page: 280-289
On-chip Test Circuits for Fast Interconnects
Rajkumar Satkuri; Marshnil Dave; M. Shojaei Baghini; and Dinesh Sharma (IIT, Bombay)
Session: 3C-4 Testing-2 Regular Paper Page: 290-300
Test Pattern Reduction by Simultaneously Pulsing Interaction Clocks
Xijiang Lin (Mentor Graphics Corp); Sudhakar Reddy (University of Iowa); and Irith Pomeranz (Purdue University)
Session: 3C-4 Testing-2 Regular Paper Page: 301-308
Adapting Scan Compression to Designs
Rohit Kapur; Anshuman Chandra; Yasunari Kanzawa; and Tom Williams (Synopsys)
Session: 3C-2 Testing-1 Embedded Tutorial Page: 309-318
Containing Switching Activity in Scan Compression
Pramod Notiyath; Tammy Fernandes; Ashok Anbalan; Santosh Kulkarni; Rajesh Uppuluri; Jyothirmoy Saikia; Glenn Boyer; Rohit Kapur; and Tom Williams (Synopsys Inc.,)
Session: 3C-2 Testing-1 Short Paper Page: 319-327


Feedback based Robust Delay Element for Low Power Designs: Design and Analysis
Sujan Manohar; and Pavan Vithal Torvi (Texas Instruments)
Session: 3A-6 Timing Regular Paper Page: 347-354
Dynamic Profiling in Virtual Prototype Environment
Praveen Kumar (NXP Semiconductors India Pvt L)
Session: 3A-6 Timing Poster Paper Page: 431
HCFG Based Approach for Evaluation of SMP Model for System-on-Chip Communication
Ulhas Deshmukh; and Vineet Sahula (Malaviya National Inst. Tech. Jaipur)
Session: 3A-6 Timing Poster Paper Page: 432-433


Case Studies Towards a Platform Independent Framework for Formal Verification of Hybrid Systems
Kusum Lata (CEDT, IISc Bangalore); Jairam Sukumar (Texas Instruments); Subir Roy (SDTC, TI India); and H.S.Jamadagni (CEDT, IISc Bangalore)
Session: 4B-4 Verification Regular Paper Page: 375-384
Functional Verification of Sleep Mode Operation in Low Power Designs at RTL
Rudra Mukherjee; Amit Srivastava; Gargi Mukherji; and Abhishek Kesh (Mentor Graphics)
Session: 4B-4 Verification Regular Paper Page: 385-394
Efficient ECO Implementation using Logical Equivalence Checking
Sarveswara Tammali; Mayank Jindal; and Shailesh Ghotgalkar (Texas Instruments)
Session: 4B-4 Verification Embedded Tutorial Page: 409-420

Keynote and Invited Talks

Teaching and Research in Microelctronics at IIT Bombay- A view from Lake Powai
A.N.Chandorkar (IIT Bombay)
Session: 2A-1 Keynote Talk

Analog and Mixed Signal Design – Need for a Curriculum Upgrade
K.Radhakrishna Rao (Texas Instruments India)

Abstract: Analog circuits are an integral part of a signal chain, since the environmental attributes that we wish to measure or control, such as ambient temperature, atmospheric pressure, relative humidity, etc., are analog in nature. This talk will look at what upgrades are needed in today’s curriculum to prepare the graduating engineer to the challenging task of designing, verifying, integrating, and testing analog circuits that are part of a system-on-chip.
Session: 2A-2 Invited Talk

Creating more Ph.D. holders in Cutting Edge Technologies
Dipankar Nagchoudhuri (DA-IICT, Gandhinagar)
Session: 2A-3 Discussion

Enabling Systems on a Chip to Test Themselves
Jacob A. Abraham (The University of Texas at Austin)

Abstract: Advances in semiconductor technology have enabled the integration of digital,mixed-signal, and RF systems on a single chip. While Systems on a Chip (SoCs) offer many benefits in cost and performance, they pose significant challenges for testing after manufacture. This talk will describe a novel approach which uses the computational resources within the SoC to test itself. The embedded processor in the SoC can test itself by running instruction sequences from memory. The tests can target classic "stuck-at" faults as well as small delay defects which are becoming more common in scaled technologies. Techniques developed recently for generating instruction sequences which have very high coverage for path delay faults in the processor will be described.
The processor can then be used to test other cores in the SoC, including mixed-signal cores for analog and RF specifications. An approach to testing data converters by putting them in loopback mode will be described. On-chip sensors which can be used to test RF modules will also be discussed. Masurements have been performed on prototype hardware and integrated circuits, and results show that the approach can predict the specifications of the mixed-signal modules with high accuracy, enabling low-cost manufacturing test.
Session: 3A-1 Keynote Talk

Electronic Design Evolution in India and its Impact on Semiconductor Design
Sudip Nandy (Wipro Technologies)

Abstract: The electronic design ecosystem has been changing in India. With the faster growth of electronic product consumption and setup of more semiconductor design groups (both captive and non-captive), we see lot of demand and opportunities for local product creation. How does it impact the semiconductor development/engineering community? What are the new skills or capabilities that would be more important in this scenario?
With the new dynamics increasing the need for companies to focus on technology domain expertise, systems understanding in addition to the challenges of doing design and the rising importance of verification at lower geometries, what are the next steps for the Indian semiconductor firms?
Session: 3C-3 Keynote Talk

Physical Design EDA Challenges for 32nm and Beyond
Mysore Sriram, Intel

Abstract: With the 32nm era fast approaching, new challenges to EDA tools are surfacing, especially in the physical design arena. Several process trends become critical at this process node, such as interconnect scaling, layout design rules and statistical variability. Each of these trends has significant implications for EDA tools. Interconnect scaling, and the resultant exponential increase in the need for repeaters, causes major issues for logic synthesis, standard cell placement and chip-level integration. The complexity of new OPC-friendly layout design rules has profound impact on routing algorithms, and stresses the need for manufacturing awareness earlier in the design process. Similarly, manufacturing-induced variability necessitates more robust clock distribution approaches and statistical design concepts built into EDA tools to prevent excessive guardbanding. This talk will explore some of these themes and current research in these areas.
Session: 4A-1 Keynote Talk

Innovation Opportunities in Biomedical Electronics
Shekar Rao (Texas Instruments Dallas)

Abstract: New Opportunities for Biomedical Electronics System innovation exist and the intersections of Healthcare and IT; Medicine and IT; Biology and IT. The talk highlights the major clinical problems in the world, for which biomedical electronics and semiconductor chip solutions wil play an important role.
Session: 3B-2 Biomedical Electronics Invited Talk

Connected Healthcare
Dinesh Bhatia (University of Texas at Dallas)

Abstract: Recent advances in low power design and increasing demand for effective technology enabled solution for managing diseases as well as general health is resulting in pervasive patient monitoring solutions. This talk will introduce various solutions for disease management, continuous patient monitoring in hospital and home environments, as well as long term patient health record maintenance.
Session: 3B-2 Biomedical Electronics Invited Talk

Moving Event Localization using Multihop Cellular Sensor Networks
Uday B.Desai( (IIT Bombay)

Abstract: The ubiquitous use of mobile phones motivates the idea of participatory sensing with a multihop cellular sensor network. In this talk we consider a moving event which is defined at any instant by the center of event (COE) occurrence and radius of influence (Re). The aim is to determine the trajectory of the moving event using sensed data obtained from mobile cell phone nodes that are located within the radius of influence. The data among cell phones is communicated in a multihop manner and not in the conventional centralized manner. On-the-fly aggregation and routing protocols are required for moving event localization using multi hop cellular sensor networks. The main contribution of this work is a novel Distributed Velocity-Dependent (DVD) Waiting Time based moving event localization protocol. In the proposed protocol, the duration (Waiting Time) for which a node needs to wait to receive data from other nodes for aggregation or relaying is determined from its local position and velocity. We also propose a Cluster-Head (CH) based moving event localization protocol, where a cluster head (CH) is elected in a distributed manner for each zone in a zonal architecture. We compare the proposed DVD and CH protocols with a modified Randomized Waiting (RW) time data aggregation protocol for moving event localization problem.
A brief mention will be made of other research, in the area of Multihop networks, pursued at SPANN Lab., IIT-Bombay.
Session: 3A-3 Invited Talk

System Verilog for VLSI design - prospects and challenges
N.S.Murty (NXP Semiconductors India)

Abstract: As designs grow in size and complexity, the challenges associated with the growing design and verification gap have created the need for a paradigm shift in the IP and SoC design and verification methodology from the traditional approaches. SystemVerilog provides a number of advantages including design specification at a higher abstraction level, code reuse and unified design and verification. Its advanced design constructs yield more compact RTL code, typically a two-to-four times reduction in the RTL lines thereby reducing coding errors and increasing the design productivity. SystemVerilog achieves improved design specification describing more functionality using less lines of code. This is done by allowing the related functionality to be described as a single object. SystemVerilog constructs allow the designers to express the intent clearly in a way the simulation and synthesis tools can have a unified view of the RTL. Assertions in SystemVerilog can be used to specify and validate the design behavior. This presentation will highlight the benefits of using SystemVerilog for design through a reference design as case study.
Low Power Verification - overcoming the challenges
Srikanth Jadcherla (Synopsys Inc.)
Abstract: The advent of LP design brings forth an explosion in the verification space to cover : new power intent files, states, transitions, sequences etc. need to be verified in a productive and accurate manner. The tutorial will dwell into these changes in the context of verification flow. We will also look at topics for research for academia in this area briefly.
Session: 3C-3 Invited Talk

Design Methodology for a 2.5GHz Native Quad Core x86 Processor
Prasad Kuppa, AMD

Abstract: Microprocessor innovation is at crossroads. Relentless push towards frequency as a single vector has imposed challenging design constraints and cost. In this talk we will discuss about Soc challenges of designing multi-core processors and correct by construction methodology to address GHz designs with considerations to improving perf/watt (Power efficiency).
Session: 4B-2 Technology-1 Presentation

Presentation by ARM Embedded Technologies
Jayanta Lahiri, ARM
Session: 4C-2 Low-power-1 Presentation