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11th VLSI Design And Test Symposium
VDAT2007

August 8-11, 2007
Convention Centre, Saha Institute of Nuclear Physics, Kolkata
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Analog Design

Design of Synchronous Buck Converter Employing an Adaptive Zero Voltage Switching for Ultra Low Power Systems
Sandeep Mehra and Bharadwaj Amrutur, Indian Institute of Science, Bangalore

A 2.4 GHz Low-voltage CMOS Low Noise Amplifier with 32 dB Gain
Anuradha Ray, ST Microelectronics and Chetan Parikh, DA-IICT, Gandhinagar

Design and implementation of a 14-bit 200 MSPS Current Steering DAC using GM/ID Method
Ramasamy Srinivasan, Venkataramani Balasubramanian and Sreekanthbabu Nukaraju, NIT Tiruchirappalli

Low-power High Slew-rate Adaptive Biasing Circuit for CMOS Amplifiers
Chetan Parikh and Narayana Rao, DA-IICT, Gandhinagar

Design of High Performance Current Steering DAC using Pattern Search Algorithm
Sreekanthbabu Nukaraju, Ramasamy Srinivasan, and Venkataramani Balasubramanian, NIT Tiruchirappalli

Power Supply Detection Circuit
Dharmaray Nedalgi and Mukesh Nair, NXP Semiconductors

VCO Phase Noise Improvement Techniques
Ravi Kumar, IBM, Narendra Bolabattin, Qualcorelogic and Eapen Abraham, Cornet Technology India

Development of an FPGA based Smart Computing System for Clinical Diagnosis with On-board Wireless Communication Interfacing
Shubhajit Roy Chowdhury and Hiranmay Saha, Jadavpur University

Design and Simulation of Integrated VCO for SMART Nanoporous Silicon Based Biosensors
Chirasree Roy Choudhury, Subhashis Sinhababu, Bengal Engineering and Science University, Shibpur, J.Kanungo and H.Saha, Jadavpur University


Circuits

A Power Efficient Carry Break Adder Implementation using Input Pattern Based Area Reduction Technique for Adder Structures
Krashna Nand Mishra, DA-IICT and Subash Chandra Bose, CEERI

Area Efficient Bit-Serial Architecture for Polynomial Basis Multiplication over Galois Fields GF(2m)
Hafizur Rahaman, Prasenjit Ray, Debasis Mitra and Amit Datta, School of VLSI Technology, Bengal Engineering and Science University, Shibpur

A Bus Encoding Technique for On-Chip Propagation Delay Minimization
Nallamothu Satyanarayana, Adams Engineering College, A Vinaya Babu, JNTU Hyderabad, Madhu Mutyam, IIIT Hyderabad

A Double-Pulsed Latch Flip-Flop
Navaram Kumar, Rajendra Patrikar, and Kishore Kulat, VNIT Nagpur

Design of Flip-Flops with Low Setup and Hold Times across Process Variations
Pratap Das, Bharadwaj Amrutur, Indian Institute of Science and Sridhar J., Texas InstrumentsIndia

A Novel Approach for Power Pad Layout generation
Venkat Vallapaneni, Raghunatha Lakkireddy, Sireesha LNVS Tulluri, and Srinivasa Gandi, Agere Systems


Design Techniques

Modified Data Encoding Circuit for Asynchronous FIFO Design
Roy Paily and Krishna Chaitanya, IIT Guwahati

Design and Simulation of a CMOS Instrumentation Amplifier for signal conditioning of MEMS based Piezoresistive Low Pressure Sensor
Niteen Futane, Shubhajit Roy Chowdhury, Hiranmay Saha, Jadavpur University and Chirasree Roy Choudhury, ETCE Dept. BESU

Effect of Inductance on Wire-Sizing the Global Interconnect in VLSI Circuits
Ashwani Kumar, Surender Soni, and Ashok Kumar, NIT Hamirpur

Circuit Prospects of DGFET: A Variable Gain Differential Amplifier With Currentmirror Load
Srimoyee Sen, Urmimala Roy, Chandan Kumar Sarkar, Jadavpur University, Chaitanya Kshirsagar and Navakanta Bhat, IISc Bangalore


Design for Testability

Layout-Aware Illinois Scan Design for High Fault Coverage
Shibaji. Banerjee, D. R. Chowdhury, IIT Kharagpur and B. B. Bhattacharya, ISI Kolkata

Compression-Power Trade-off in Dictionary based Test Data Compression
Chandan Giri, Nikhil Reddy Cheruku and Santanu Chattopadhyay, IIT Kharagpur

Fault Diagnosis in Reversible Circuits
Bikromadittya Mondal, BPPIMT, Susanta Chakraborty, Bengal Engg. and Science University and Bhargab Bhattacharya, Indian Statistical Institute

Using Hierarchy in Design Automation: The Fault Collapsing Problem
Vishwani Agrawal, Auburn University and Raja Sandireddy, Intel Corporation

Testing Droop Faults in Full Scan Circuits
Debasis Mitra, Bengal Engineering and Science University, Shibpur, Howrah, Ashish Nigam, Sandeep Dey, Susmita Sur-Kolay, and Bhargab Bhattacharya, Indian Statistical Institute

A New Approach for Testing of Digital Modules in Mixed Signal VLSI Circuits
Santosh Biswas, M Rajaneesh, R. Bhattacharya, S. Mukhopadhyay and A. Patra, IIT Kharagpur

Detection of Single Stuck-at and Bridging Faults in Cluster-based FPGA Architectures
Sudip Ghosh, Marine Engineering and Research Institute, Kolkata, Nachiketa Das and Hafizur Rahaman, School of VLSI Technology, Bengal Engg. & Science University, Shibpur

Genetic Algorithm based Test Scheduling for Network-on-Chip
Santanu Chattopadhyay, Mahalakshmi Satti, and Santanu Kundu, IIT Kharagpur


EDA

An Algorithm for Resistance Extraction and Current Density Profiling of Lateral Power MOSFETs
Baidurya Chatterjee, Syamantak Das, Amit Patra, IIT Kharagpur and Samrat Ray, Cadence Design Systems, Noida

An Error Comparison Scheme for Design Rule Checking Flows
Dibyendu Goswami and Swami Gangadharan, Intel

Delay Clock Methodology for Timing-Performance Improvement of Designs on FPGAs
K. Vinay, R.D. Singh, S. Maleka, Kamakoti Veezhinathan, IIT Madras, and Anirban Rahut, Xilinx Corporation, USA

Crosstalk Noise Analysis Tool and Development of an Automated Spice Correlation Suite to Enable Accuracy Validation
Venugopal Chakravarthy, Jagannath Rao, SJ College of Engg and Prashanth Souraiyur, Texas Instruments India

Voltage Scalable Statistical Gate Delay Models Using Neural Networks
Bishnu Das, Bharadwaj Amrutur, Indian Institute of Science and H.S.Jamadagni, CEDT, IISc, Bangalore

Fast I/O Pad Placement in FPGAs
Debasri Saha, Pritha Banerjee, and Susmita Sur-Kolay, Indian Statistical Institute, Kolkata

Crosstalk Analysis for a CMOS Gate Driven Coupled Interconnects
Brajesh Kaushik, Ramesh Joshi, IIT Roorkee, Sankar Sarkar, MITS, Sikar, Rajendra Agarwal, Bundelkhand University, Jhansi, U.P


Low-power

CV-based Analytical Modeling of Dynamic Power for 65nm CMOS Library Characterization
B.P.Harish, University Visvesvaraya College and Navakanta Bhat, ECE, Indian Institue of Science, Bangalore

A Novel Efficient Power Optimization Method for Off-Chip Memory Access using Differential Memory Addressing
Sajal Kumar Das and Rangaramanujam Srinivasan, Texas Instruments India

Leakage Modelling of Logic Gates Considering The Effect of Input Vectors
Janakiraman Viraraghavan, Bishnu Das, Bharadwaj Amrutur, Indian Institute of Science and Vish Vishwanathan, Texas Instruments India

Leakage and Switching Power Minimization with Area Trade-off in Multiplexer Based Circuit Synthesis
Sambhu Pradhan and Santanu Chattopadhyay, IIT Kharagpur

A Novel Toggle-less, LUT-less Low Power Distributed Arithmetic (DA) Architecture for FIR Filter
Uma Rajaram, Professor and Augusta Sophy, Easwari Engineering College

A Core Power Pad Planner for Wirebond SoCs
Jairam Sukumar, Udayakumar H, Texas Instruments, Rajat Chopra, and Kousik Mukherjee, Interra Systems, Noida

Design of an Application Specific Low-Power High Performance Carry Save 4-2 Compressor
Anup Dandapat, Partha Bose, Sayan Ghosal, Pikul Sarkar, Animesh Biswas, and Prof. D Mukhopadhyay, Jadavpur University

Power Optimized Machine Code Generation for an Application Specific Instruction Set Processor (ASIP) for Hindi Text to Speech Synthesis
Atanendu Mandal, CEERI and Sanjay Singh, Student Trainee, Kurukshetra University

Implementation of SPIHT Codec In Stratix-II
Gunvanta Mate, Kishore Bachina, K Ramesh, and J. Anbuselvi, CRL-BEL, Bangalore
FPGA Implementation of Low Power ASU Multiplier
Rahul Badghare, Sanjiv Mangal, Raghvendra Deshmukh, and Rajendra Patrikar, VNIT, Nagpur

Improved Reversible Logic Implementation of Decimal Adder
Rekha James, Shahana T K, K. Poulose Jacob, CUSAT and Sreela Sasi, Gannon University


MEMS - Technology

Fabrication of MEMS PZR Accelerometer for Automobile Application
Ravindra Mukhiya, I. S. Bajpayee and S. Kal, IIT-Kharagpur

Bulk-Micromachining for MEMS Accelerometer using 25% WT. TMAH
Ravindra Mukhiya, S. Kal, IIT-Kharagpur and M. Zen, Microsystems Division (MIS), ITC-irst, Trento, Italy

Design, Modeling and Simulation of High Performance RF MEMS Switch for Phase Shifter Applications
Avra Kundu, Swati Majumdar, Bhaskar Gupta, and Hiranmay Saha, Jadavpur University

Characterization of Universal Nand-Nor-Inverter QCA gate
Biplab Sikdar and Bibhas Sen, BESUS


Systems

Dual Encoded Gray Coding Scheme
Salil Gadgil and Senthilkannan Chandrasekaran, Texas Instruments

Incremental Connectivity Extraction for Large VLSI Layouts
Akash Agrawal, IIIT Hyderabad

Latency Optimized AES-Rijndael with Flexible Mode of Operation
Monjur Alam, Santosh Ghosh, Dipanwita Roy Chowdhury, Indranil Sen Gupta, IIT- Kharagpur and Debdeep Mukhopadhaya, IIT - Madras

On the Realizability of Specifications having Auxiliary State Machines and GR(1) LTL
Ansuman Banerjee, Pallab Dasgupta, and Partha Chakrabarti, IIT Kharagpur

A Transformation Based Method for Formal Analysis of Hybrid Systems
Jairam Sukumar, Subir Roy, Texas Instruments India and Navakanta Bhat, ECE, Indian Institue of Science, Bangalore

Hybrid Masked Karatsuba Multiplier for GF (2233)
Chester Rebeiro and Debdeep Mukhopadhyay, IIT MADRAS

Priority Queue based LRU Models for Associative Cache
Vijayalakshmi Seshadri, Airvana Networks India Pvt Ltd

A New Spice Simulator for Single Electron Transistor Based Integrated Circuits
Biswajit Ray, Ashish Pal, Saptarshi Das, and Santanu Mahapatra, Indian Institute of Science

A Lifting based Reconfigurable forward and Inverse Discrete Wavelet Transform Architecture for JPEG2000
Yogesh Inamdar and Ramesh Kini, N.I.T.K., Surathkal

MOTSOC: Mesh of Tree based Network-on-Chip Design A New Interconnection Structure for SOCs
Santanu Kundu, Santanu Chattopadhyay, and Mahalakshmi Satti, IIT Kharagpur

State Encoding Targeting Low Area and Low Power FSM Synthesis
Santanu Chattopadhyay, Saurabh Chaudhury, and Krishna Sistla, IIT Kharagpur


Technology

A Simulation based Study and Analysis of Double Gate Tunnel FET Performance for Low Standby Power Applications
Nayan Patel and Santanu Mahapatra, Indian Institute of Science, Bangalore

Multilevel Pyramidically Wound Symmetric Spiral Inductor
Genemala Haobijam and Roy Paily, Indian Institute of Technology Guwahati

Floating Gate Interferences on Vth Distribution In Eight Level High Density Flash Memory
Roy Paily, Vikas Badam, IIT Guwahati and Yajun Ha, National University of Singapore


Test - Verification

Debugging Assume-Guarantee Specification for Compositional Verification
Anindyasundar Nandi, Interra Systems India Pvt Ltd, Bhaskar Pal, and Pallab Dasgupta, IIT Kharagpur

Formal Verification of Pipelined Read-Modify-Write Logic by Generalized Symbolic Trajectory Evaluation (GSTE)
Subir Roy, Texas Instruments India, Srikanth Reddy and Bharadwaj Amrutur, Indian Institute of Science

An Efficient Implementation of Testbench for Verification of Configurable Host Controller IP Addressing Mobile Storage Applications
Pusuluri Giri Kumar, Synopsys (India) Pvt Ltd

Scenario Driven Test Case Generation for Functional Verification of Pipelined Processors
Subrat Panda, Venu Gopal Kasturi, and Partha Chakrabarti, IIT Kharagpur

Dcache and Icache Memory Testing Using CPU BIST
Sourabh Saluja and Vijay Sindagi, Texas Instruments

Co-simulation: Verification Advantage with PCI Express Endpoint SystemC Model
Aditya Ayre, Aniket Deshpande and Vishal Rustagi, CDAC-PUNE

Case study: Reducing Run time of Volume Diagnosis by Using Reduced Pattern Set and Truncated Failure Log
Dhiraj Maheshwari and Ravi Dasari, Mentor Graphics

Formal Verification of a Fast DMA Controller: A Case Study
Anindyasundar Nandi, Bijitendra Mittra, Interra Systems India Pvt Ltd, Subir Roy, and Prohor Chowdhury, Texas Instruments India


Embedded Tutorials

The Next Step in the SoC Design Automation
Manikandan Panchapakesan and Ramachandra Vibhute, NXP Semiconductors

Formal verification of DFT logic and their integration in SoCs practices, issues and challenges
Subir K. Roy, Texas Instruments, Bangalore, A.S. Nandi and Bijitendra Mittra, Interrasystems, Kolkata

Game Theory and its Application to VLSI Physical Design
Parthasarathi Dasgupta, IIM Calcutta

Addressing Test Power Issues in Digital CMOS Circuits
Srivaths Ravi, Texas Instruments India

Strategies for Power Reduction during VLSI Circuit Testing
S. Chattopadhyay, IIT Kharagpur

Challenges posed to the State of the art device Simulators in Nanoscale Regime
Shubhakar K, Biswajit Ray and Santanu Mahapatra, Indian Institute of Science, Bangalore

Design Approach for Standard Single Ended Input Output Buffer in 65nm Process
K S Raghunathan


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