6th VLSI Design And Test Workshops

August 16-18, 2001
JN Tata Auditorium, IISc, Bangalore
Please visit VSI publications for details on VDAT proceedings.
Search for paper details and abstracts

Formal Verification

Mechanical Verification of Microprocessors
Mandayam Srivas, Realchip, Chennai, India

Rapid System Prototyping
Suryanarayana Adiga and Vinay Shenoy, Philips Semiconductors, India

Designing Multi-million gate FPGAs
P. Wikneswaran, CGCoreEl, India

SOC Design Strategy
Veena S. Chakravarthi & Vilas Bhade, Mindtree, and Guru Murthy, UVCE

Test Generation

Parallel Guided Genetic Algorithm based Test pattern Generator using Message
M.C. Bhuvaneshwari, S. N. Sivanandan, Deno Mathew, G. Sundramurthi, PSG College, Coimbatore, India

Functional Test Generation of a Pipelined Implementation of DLX Processor
Ragahvendra Kulkarni, Vivek Agarwal, IIT Delhi, Rajiv Nadig, Analog Devices, India, and C.P. Ravikumar, Controlnet, India

Reordering Test Patterns with Don't Cares for minimizing power during Combinational Testing
Santanu Chattopadhyay, IIT Guwahati

Architecture for Programmable Memory BIST
Rubin A Parekhji, Texas Instruments India, Ravindra Saraf and Arun N. Chandorkar, IIT Bombay


Partial Scan Design With Guaranteed Combinational ATPG
Vishwani Agrawal, Agere Systems, USA, Yong C. Kim and K.K. Saluja, U. of Wisconsin, Madison

Design Tradeoffs in Logic BIST
K. Nikila, Jais Abraham and Rubin A Parekhji, Texas Instruments India

A testable design for detection of path delay faults using DSTL Array
H. Rahman, A.P.C. Roy Polytechnic, Calcutta, D. Das, Jadavpur University, and B. Bhattacharya, ISI Calcutta

SoC Testing

Telecom System-On-Chip Testing
David Khanna and R. Madhu, Texas Instruments, India

Test Strategy for Next Generation System on Chip (SOC): Case Study Ethernet
B. Suresh, Vinod Menezes, Phani Kumar, and George Smolinski, Texas Instruments India

Design Closure

Electrical Design Closure: A Review of the Sate-of-the-Art and Challenges. Invited Talk
V. Arvind, K. Sampath, P.R. Suresh and V. Visvanathan, Texas Instruments, India

Digital Signal Processing

An Area-efficient Bit-Serial FIR Filter Architecture
Puneet Goel, Motorola, Gurgaon, India

A methodology for Opcode Assignment to Reduce Area and Delay of Instruction Decoder
Subash Chander G and Ajit Gupte, Texas Instruments, India

Design of RF CMOS Phase-Locked Loop and Frequency Synthesizer
S. Ali and Faquir Jain, Univ. of Cincinnati

System-level Design

A Comparison of USB and Firewire
Amey Hegde, Controlnet India, Goa

A Hierarchical Approach for Detecting Naming Incompatibilities in Design Database
Nirav Patel and G. N. Nandakumar, Agere Systems, India

Low Power Design: Abstraction Levels and RT Level Design Techniques
Rajeshwari Banakar, Ranjan Bose, and M. Balakrishnan, IIT, Delhi

A stochastic scheduling algorithm for Real-time Systems
Shampa Chakraverty, NSIT, New Delhi and C.P. Ravikumar, Controlnet (India)

Fuzzy Sets for IP Core Compliance Levels
SuteekshnKumar, Infineon Technologies India, Bangalore

EDA software - Where quality is not a wish but a must!!
R. Raghuraman, Texas Instruments, India

New Horizons in VLSI Technology

Optoelectronic Integrated Circuit (OEIC) Receivers
P. Chakrabarti, Banaras Hindu University

Design Techniques

Comparative Performance of Ring Oscillators on Bulk and SOI Substrates
Andrew Marshall, Sreedhar Natarajan, and Homi Moghul, Texas Instruments, Dallas, USA

Dual Vt Technology using Dual Thickness Gate Oxide
E. Simi, S.S. Sudheer, and Navakant Bhat, Indian Institute of Science, Bangalore

Development of a Smart Humidity Sensor based on Porous Silicon
H. Saha, J.Das, S.Dey, and A. Bagchi, Jadavpur University

Low-power Standard Cell Library Development
Pankaj Rohilla and Jwalant Joshipura, ST Microelectronics, Noida, India

Alternate Flow to counter Antenna Problem in ASICs
Kamran Nabi Khan, Controlnet India, Goa

A Routing Technique for Structured Designs which Exploits Regularity. Invited talk
Sabyasachi Das, Intel Corporation, USA, and Sunil P. Khatri, University of Colorado, Boulder

TABULA: A Tabu-Search based Floorplan Area & Delay Optimizer
Parthasartathi Dasgupta, IIM Calcutta

Deep Submicron

A Two-Dimensional Simulator For Studying Ionizing Radiation Effects In Deep-SubmicronMOSFETs
Partha Chakrabarti, M. C. Gupta, P. K. Tiwari and V. Kumar, Institute of Technology, Banaras Hindu University

Some Non-Ideal Effects & Reliability Issues in VLSI Design
Rajeevan Chandel, M. Chetan, REC Hamirpur

Transitor Flaring in Deep submicron Manufacturing: Issues and Solutions
Vipul Singhal, K.G. Sumanth, C.B. Keshav, and P.R. Suresh, Texas Instruments India

Optimization of 0.1 nm transistor using Disposable Spacer Technique
Navakant Bhat and H. C. Srinivasaiah, IISc Bangalore

Design Synthesis Of CMOS Operational Amplifier From User Specification
S.C. Bose, V. Sunitha and Chandra Shekhar, CEERI, Pilani