2nd VLSI Design And Test Workshops

August 6-7, 1998
The Habitat World, Lodi Road, New Delhi
Please visit VSI publications for details on VDAT proceedings.
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M-Testable Arithmetic Iterative Arrays
M. Jamoussi, KFUPM

Automated Synthesis of Large Phase Shifters for BIST.
Janusz Rajski, Nagesh Tamarapalli, and Jerzy Tyszer, Mentor Graphics
Download PS, 67 KB

On Connectivity and Inversion Problems in Scan Chains.
Rubin A. Parekhji, Texas Instruments

DEST: A Method for Multiple Stuck-at and Delay Fault Detection in Combinational Circuits
Ashok S. Nale, Silicon Interfaces

Methodology for Static Verification of Multi-Million Gate Designs
Shekhar Saha, Synopsys (India)

Multiple Signature Testing for Path Delay Faults
Ashima Malhotra, Duet Technologies, C.P. Ravikumar. IIT Delhi

Integrated Test Vector Flow for Design QC
Chandramouleeswaran, Texas Instruments India

Test Vector Language Parser Enabling Language-Independent Test Flow
S. Baskar, Texas Instruments India

Designing a Testable IIR Filter Core
A. Sinha, P. Kaul, C.P. Ravikumar, IIT Delhi

Logic Design

Design of Digital FIR Filters for Low Power Applications
Ashima Malhotra, Duet Technology and C.P. Ravikumar, IIT Delhi

Parameterized Divider Cells for Datapath Synthesis
A. Shyamprakash, Cadence India, Ram G. Mohan, IIT Delhi

Standard Cell based and FPGA based ASIC design of CORDIC Core
Rohit Sharma, Texas Instruments

Hardware Software Partition Using Genetic Algorithms and Application to MPEG Encoder and Echo Cancellation
A.V. Pranatarthi, ICON Systems, India

Integrated Scheduling and Allocation for Synthesis of Structured Data Paths
C. Mandal, R. Zimmer, Brunel University, UK

Constraint Programming Applied to High-Level Synthesis and System-Level Synthesis of Application-Specific Systems
Y. Gavriel, Virginia Tech.
Download PS, 35 KB

Modelling and Performance Analysis of Buffered Leaky Bucket Policing for ATM Networks using VHDL
N.R. Alamelu, PSG College of Technology

Development of a large scale System Partitioner
M. Kartik, H.Narayanan, Dept. of EE, IIT Bombay

System Partitioning and Technology Selection
A. Srivastava, S. Gupta, C.P. Ravikumar, IIT Delhi, Chandrashekhar, CEERI, Pilani

VLSI Design Flow Management
V. Sahula, IIT Delhi

Hardware-Software Cosynthesis of a Multiprocessor System for Real-time Applications
S. Chakraverty, Delhi Institute of Technology

VLSI Design Experience at Kurukshetra University
Sanjeev Sablok, Dinesh Kumar, Anil Vohra, P.J. George, Kurukshetra Univ.

Physical Design

A Fast Algorithm for Transistor Folding
Edward Y.C. Cheng and Sartaj Sahni, University of Florida

Wire Length Minimization in Multi-layer Channel Routing
R.K. Pal, S.P. Pal, A.Pal, University of Calcutta

Crosstalk Minimization through Transistor Sizing
Sacheendra Nath, C.P. Ravikumar, IIT Delhi

Fast Circuit Extraction from MOS Switch-level Descriptions
Debashis Sarkar, Motorola India Electronics Ltd., B.B. Bhattacharya, ISI, Calcutta

Effective Capacitance Seen by Timing Arcs in a Cell
Soumendra Nath Mandal, Anurag Seth, Duet Technologies

Topological Routing in the Presence of Polygonal Obstacles
P. Mahalingam, S.C. Nandy, B.B. Bhattacharya, ISI, S. Sur-Kolay, Jadavpur Univ.

Dielectric Based Electrostatic Microactuators.
Rajeevan Chandel, REC Hamirpur

CMOS to TTL interfaces in high performance VLSI circuits
R. Krishnan, Cypress, India

Placement Algorithm for Low Power
P. Gupta, Synopsys India

VLSI Chips on 3-D Closed Surfaces.
Satrajit Ghosh, ISI Calcutta, B. Bhattacharya, ISI Calcutta, and S. Sur-Kolay, Jadhavpur University
Download PS, 140 KB

Reliability Problems in Deep Submicron ICs
Team from Analog Devices, India