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|June 27, 2005: VTU, VSI and ISA sign an MoU.
February 24, 2006: First VTU-VSI-ISA Confluence meeting held at Bangalore.
VSI Election 2011-2012
8 August 2011: VLSI Society of India conducted an election to constitute new office bearers for the post of President, Secretary and Treasurer. The newly elected office bearers for the term:
President: Dr.Jaswinder Ahuja,
Cadence Design Systems - (Aug 2011 - Present)
Secretary: Jayanta Lahiri
, ARM India - (Aug 2011 - Present)
Treasurer: Sathya Sargunesan
, ARM India - (Aug 2011 - Present)
7 July 2011: VLSI Society of India is holding election to constitute new office bearers for the post of President,Secretary and Treasurer. Present members are notified individually. Download the Ballot form
(PDF 54 kb) and send it filled before July 23, 2011. Results will be announced on VSI website.
Industry-Academic Confluence Meeting at Bangalore
Feb 24, 2006: The VLSI Society of India signed an MoU with the Visweswaraya Technological University (headquartered at Belgaum, Karnataka) and the India Semiconductor Association in June 2005 in order to spread and improve the quality of VLSI Education. Under the aegis of this MoU, colleges that offer M.Tech programs in VLSI Design and Embedded Systems have been identified as centers where champions from the industry will work in close cooperation with faculty champions to improve the quality of M.Tech programs.
Read more reports about VSI-VTU-ISA confluence held on April 28, 2006 at Belgaum, Karnataka:
(Scanned images of Newspaper clippings that open in a new browser Window)
VTU, ISA ink agreement on interaction
April 30, 2006 - Vijay Times
Meet on semiconductors held
April 30, 2006 - Hindu
VTU signs MoU with ISA
April 30, 2006 - Indian Express
The portal of VLSI Society of India is updated to http://vlsi-india.org/vsi
from mid-June, 2006.
VSI In the Press:
Press coverage for VDAT 2007
Press Report: 14th VDAT 2010 Symposium; July 7-9, Chitkara University Campus, Himachal Pradesh (PDF 500KB)
EE Times: Design News
India team unveils new approach to test digital modules
(09/17/2007 11:10 AM EDT)
BENGALURU, India — A team of researchers at the Indian Institute of Technology in Kharagpur have developed new approach for testing digital modules embedded in mixed-signal VLSI circuits.
The team's methodology was based on analog backtrace, a technique that uses analog blocks themselves to test digital blocks. The methodology stresses the controllability of the inputs of the digital block by exploiting the analog block.
In a paper presented in the VLSI Design and Test 2007 held here, the team said its results were based on work done at the transfer function level. However, transistor-level simulation of analog circuits must be performed for a more realistic study, and it is on this aspect that the team is now working, the researchers said.
The investigators contend that, although problems in automatic testing and test pattern generation for digital circuits have been solved, directly applying and observing test patterns and responses is not possible when digital blocks are embedded in between analog blocks, as in mixed-signal ICs.
The team developed a methodology that enables it to exploit the analog circuits themselves to test embedded digital blocks with as little overhead as possible. They addressed the first problem in testing digital modules in mixed-signal circuits (treating the analog blocks as ideal). Next, parameter variations in the analog block were considered for developing an effective test solution. The effectiveness of the technque were verified by simulation of some analog benchmark circuits.
"Recent improvement in fabrication technology has made possible the realization of ICs containing both analog and digital functions on the same silicon. The problem of testing digital cores in the circuits is, however, more complicated than that of testing purely digital cores," the researchers said.
Because the analog blocks have direct access to the digital cores through quantizers, and because the team controlled the analog block directly, discrete Fourier transform overheads were minimized, the researchers said. "Our proposed test methodology emphasizes the controllability of the input of the digital block by exploiting the analog block."
The team said their results obtained were encouraging when work was carried out at the transfer function level. Transistor-level simulation of analog circuits will be carried out next. The algorithm also needs to include nonideal analog/digital interfaces.
EE Times: Design News
India launches new VLSI design initiative
(06/14/2006 10:45 AM EDT)
BANGALORE, India - The Indian government has launched a VLSI education program across 32 institutes to increase the availability of chip design talent. The $10 million, five-year program is meant to supplement a similar program launched in the late 1990s.
The new program will focus on developing four streams of engineering manpower to meet growing demand for design engineers from technology companies expanding here. New VLSI design labs with advanced EDA tools are also planned.
The first stream will focus on doctorate-level VLSI design and related software development. The next will look at generating post-graduate engineers in VLSI design and microelectronics. A third will boost the number of post-graduate engineers in electronics and computer science with VLSI design as an elective subject. Finally, a program will provide graduate engineers with exposure to VLSI design, according to India's Ministry of Information Technology.
The plan, which is expected to generate a total of 2,500 qualified design engineers annually, is designed to help India grab a larger share of the global design market, the government said.
Press coverage for VDAT 2006
EE Times: Design News
Indian researchers unveil processor test framework
(09/08/2006 11:19 AM EDT)
BANGALORE, India - Researchers from the Indian Institute of Technology in Chennai and Intel's validation and test solutions center at Austin have teamed to unveil a unified framework for generating functional tests for processors, at the recent VLSI Design and Test 2006 conference in Goa in western India.
"The framework can be used to generate directed test for functional verification of processors, at different levels, namely, the Instruction Set Architecture to Micro-architecture, and also combinations of them," the paper said. "A constraint solver-based approach is employed in the framework. The effectiveness of the framework is demonstrated by developing the same using the ILOG Constraint Solver and plugging-in Cache and Translation Look-aside Buffer (TLB) models into it," the paper added.
One benefit of the framework is the plug-and-remove feature it offers for different modules, useful for evolving designs where design development and verification are done concurrently, the paper said.
The methodology proposed is scalable with the design size, as this involves development of constraint model-based on the design specification, which is at a higher level of abstraction. The constraint model thus designed is an integration of several sub modules which are derived, based on the functionalities of the design, such as the TLB, cache, and branch predictor, which leads to a natural partitioning of top-level constraint model, aiding scalability.
EE Times: Design News
Indian researchers propose new SoC test method
(09/12/2005 10:54 AM EDT)
BANGALORE, India - With efficient test access architecture of much interest to the SoC design and test community, two researchers at an Indian technical institute have proposed a design-for-test method for digital SoC designs using a Test Access Mechanism (TAM) switch.
Shibaji Banerjee and Dipanwita Roy Chowdhury of the Indian Institute of Technology, Kharagpur, have developed a new test strategy algorithm to exploit the possible parallelism of testing the cores. The algorithm generates the needed TAM switches, the configuration information of all the TAM switches and also TAM-to-Core connection need for the SoC under test.
A new computer aided test (CAT) tool has also been developed to test the SoC designs, they said.
In a sequential core, only scan chains are considered for testing as flip flops are more defect prone, so no extra hardware except the TAM switch is needed for the test. The benefit of considering only scan chains is that they can be tested in parallel. The test access mechanism is implemented on-chip by using a special TAM switch, and a synthesizable RTL core can be instantiated in a design to provide test access data to embedded cores in the SoC.
The TAM switch is a programmable cross bar switch allowing efficient delivery of test vectors to embedded cores at varying bandwidth. It has two useful operational modes-- in the cross configuration the switch is configured to send the test patterns to the core-under-test. while in the pass configuration the switch passes the test patterns to the next switch.
The proposed scheduling algorithm is divided into that for sequential cores in the SoC, another for combinational cores in the SoC and a third for the SoC with both sequential and combinational cores. During scheduling, the higher priority nodes are scheduled first, based on lower label nodes having higher priority than those with higher labels, while among nodes having the same label nodes with higher weight get priority.
The proposed scheduling algorithm has been implemented and experimented on the ITC ’02 SoC test benchmark; the experiments were done on Sun Sparc Ultra 60 workstation in Solaris 5.8. The new CAT tool has been demonstrated for the ITC ’02 test benchmarks. The experiments showed significant reduction of the time taken for system-level testing, the researchers said.
News and New Products
Global Designer: Indian semiconductor companies upgrade engineering skills
By Chitra Giridhar, EDN Asia -- EDN, 9/15/2005
Experienced chip designers are becoming an increasingly scarce commodity, as vendors outsource more work to the Indian semiconductor industry. "There is a dearth of design engineers with a combination of electronic-design skills and an adequate knowledge of the latest tools," says G Satish Kumar of Mentor Graphics Sales and Services. To plug the gap, companies such as ATI, Magma, Mentor Graphics, and TI are taking the initiative to upgrade the skills and knowledge of local design engineers. Collectively, the companies spend more than $1 million a year-either in the form of monetary contributions for education or by providing software and tools for design labs in universities. "There is an acute shortage of VLSI front- and back-end-design talent," says Dasaradha R Gude, managing director at ATI Technologies India. Consequently, ATI is collaborating with Hyderbad-based Veda IIT on diploma and master's degree programs for design engineers. "We have trained more than 1000 engineers on the entire Magma flow," comments Anand Anandkumar, managing director of Magma Design Automation India. "Talent that can develop EDA tools and analog ICs is in short supply."
"There is a huge gap between what the universities teach and what the industry requires," confirms Professor K Jayaraman, chief mentor at CICT Pvt Ltd, adding that universities lack the resources for developing labs or to invest in software tools. "The lack of a coordinating body is a problem," says CP Ravikumar, PhD, secretary of the VLSI Society of India. To bridge this divide, the ISA (India Semiconductor Association) and VSA (VLSI Society of India) have launched a pilot program with Belgaum-headquartered VTU (Vishvesvaraya Technological University). "The initiative encompasses research, curriculum, and faculty development, EDA-tool support and ecosystem creation," says Poornima Shenoy, president of ISA. The pilot program will create opportunities for greater industry-academia interaction, create an industry-oriented curriculum, and facilitate the infrastructure to support the programs.
EE Times: Design News
India creates semi, EDA research consortium
(08/10/2005 1:21 PM EDT)
BANGALORE, India — Expanding its efforts in electronics, the India Semiconductor Association (ISA) on Wednesday (Aug. 10) announced plans to create a new semiconductor and electronic design automation (EDA) research consortium. The ISA will create the so-called Semiconductor Research Consortium for India in an effort to increase industry-oriented research and facilitate EDA software acquisition in some of the nation’s institutes. It will also create and support industry-oriented student projects and increase student placement into semiconductor firms.
The ISA also continued its push to expand engineering education. The organization unveiled its University Gateway Initiative in partnership with the VLSI Society of India (VSI).
The ISA also signed a memorandum of understanding agreement with the regional body for engineering education, the Visvesvaraya Technological University (VTU).
The VTU oversees Karnataka state’s engineering education, including Bangalore, the state capital, and with 120 institutes. This deal is expected to propel recruitment for the growing design services industry in the country.
“Talent generation is central to the Indian semiconductor industry’s effort to move up the value chain and gain global eminence. In our industry, a clear way for achieving this is through a ground initiative that encompasses every facet and fosters the creation of a supportive ecosystem. With this initiative, ISA has taken the lead in making it happen,” said Rajendra Kumar Khare, chairman of the ISA.
“The initiative encompasses every possible area from research, curriculum, faculty development, and EDA tool support to ecosystem creation. It covers all parties involved right from the industry bodies, companies, and academic institutions,” said Poornima Shenoy, president of the ISA.
EE Times: Design News
Indian VLSI group cites dearth of design skills
(09/07/2005 10:55 AM EDT)
BANGALORE, India - Though hundreds of thousands of engineers graduate from over 1,300 technical institutions in India, the numbers of those with VLSI design skills is meager, according to Indian industry group VLSI Society.
A survey by the group has found that that less than 1,000 students graduating with bachelor's degrees annually specialize in semiconductors/VLSI.
This means that less than one percent of graduating engineers in India have the skills the design services industry here needs. That such skills here are rare is no secret, but this is among the first surveys by an industry body, which also indicated that less than 500 master’s degree students come out annually with the necessary skills.
In the inaugural issue of the Society's newsletter, Bobby Mitra, president, VLSI Society of India and head of Texas Instruments (India) Pvt. Ltd., said a large pool of highly skilled individuals is needed to execute the increasing number of chip design projects coming to India.
"This is an area of concern for us all. How do we grow and sustain the adequate number of highly talented people to take this revolution forward?" he asked.
The number of graduates interviewed by managers before hiring one is staggering-- sometimes as high as 30. "This speaks volumes about the gap in the expectations of the industry and the output coming from academic institutions," said C.P. Ravikumar, senior technologist, Texas Instruments.
Managers' complaints range from interviewees being weak in basic concepts, inability to answer simple questions about electrical circuits and digital logic. Besides, technical institutes do not have the resources to recruit faculty, develop labs and invest in software tools. Some institutes either have no courses in semiconductor devices, circuit design and test or make these optional for students, most of whom prefer a job in application software development.
Some faculty believe CMOS circuit design, design flows, effect of interconnects, design timing, verification and testing need to be stressed. Industry appears apathetic, interested only in fresh hires, and not interacting with institutes, offering internships, student projects or research funding.
The launch of the India Semiconductor Association and its proposed joint programs with Indian universities is expected to help address the situation, Ravikumar added.
EE Times: Design News
India EEs spin seamless design flow framework
(10/06/2003 11:45 AM EDT)
Bangalore, India - With the industry lacking a single framework that can lay claim to represent the design flow from RTL to GDSII, engineers here have proposed what they call a revolutionary, seamless design flow framework.
While popular tools and subflows are available, no single framework exists, the team said in a paper at the VLSI Design and Test (VDAT) 2003 meeting here recently. Their solution is targeted for now on the physical-design aspects of VLSI but the concepts are generic and can be applied to front-end or other design flow segments as well. Abhishek Pandey, Pradeep Cavale and A. Krupakaran of Spike Infotech in Bangalore said their solution, QuickFlow (QF), provides a seamless flow to take a design from RTL to GDSII by allowing the creation of flows based on a mix of preferred tools. QuickFlow allows for efficient utilization of resources such as servers and licenses, and captures reuse within the system, the trio said.
"QF is easily customizable to new and emerging technologies like 0.13/0.09 micron and above, and to specific foundries. An expert-system-based learning is available to help users choose tools/flows for their specific purposes and project management capability is included within the system. All these features come with a Web-based control to the system for initiating and monitoring tasks. The scope for future work includes improving the learning capabilities of such a system," their paper said.
Finding from their customers that there is need for such a system as QF, the engineers said the benefits it brings are immense. QF addresses the needs of rapid design flow creation and management, archiving of reusable design flows, capture of tool/flow expertise within the system, design flow execution control and full-time monitoring of the status of design flow runs. Status information is available to designers from the flow, which is said to monitor hardware and software resources and to offer effective project management.
The QF environment is one that enables users to create and maintain a design flow with a knowledge database that grows over time. This environment controls flow execution and other aspects of typical physical-design projects. QF is billed as a fully configurable and customizable solution, in which the quality is dependent on the designers doing the configuration.
QF is accessible from anywhere through the Internet, and a built-in messenger communicates with designers by e-mail to keep them updated on the status of the flow execution. It addresses security concerns of some Web-based systems by using the Secure Sockets Layer and Message Digest 5 for encryption. It has multi-tier user management for improved project control supporting administration, managerial and designer user types.
The knowledge database, called CookBook, contains tool recipes, and is reusable across projects, since it is generic. Designers can create a flow by using recipes in the CookBook, the team said.
The system performs status monitoring of task execution, with output of tasks viewed through a Web page. When an execution is finished, an e-mail goes out to the designer with the return status. All involved can monitor project status too, the designers said. QF can also be configured to add more intelligence to the system with plug-in scripts; a scripting language has been developed for this.
QF makes it possible to distribute jobs on different servers to keep the load optimal, the three engineers said. Enhancement also ensures that the program addresses concerns of tool licenses and allows tracking of versions of design files. Metrics can also be provided to review design projects, including time spent on tasks, designer productivity and number of iterations for different branches in a flow.
Case studies indicated that QF reduces design time, the paper said, and more reductions are expected over time. QF has been used on small and medium-size designs and is being benchmarked on million-gate designs. It is now being deployed on a 0.13-micron design.
Elsewhere at VDAT, two professors at an engineering college in Coimbatore in southern India have proposed a new VLSI design for an existing routing algorithm using a parallel architecture. K. Paramasivam and K. Gunavathi said simulations showed that results obtained by using the new design prove that a routing table can be created with optimized and suboptimal paths based on reliability studies for nodes as well as the path. The pair said in their paper that while they implemented and simulated using a 17-node communication network, the simulation could be extended for larger networks with more nodes as well.
In another paper, K. Gunavathi and H. Mangalam presented a theory and algorithms for building a low-power clock tree using two low-power clock schemes: reduced swing and multiple supply voltages. New ways to cut power dissipation are needed, since the clock network can dissipate 20 to 50 percent of the total power on a chip. Ignoring static power dissipation in their study, the pair controlled short-circuit power dissipation by enforcing a constraint that the clock edge should never have a transition (rise/fall) time that is larger than a given specification throughout the clock tree. "By enforcing this sharp clock requirement, the short-circuit power is bounded and can be neglected in comparison with the charge/ discharge power," they said.
The proposed algorithm for clock tree distribution is similar to previous work in many ways, Gunavathi and Mangalam said, except that it uses an HL converter at the root of the tree and an LH converter at various points in the clock tree. Tests showed power savings of an average of 45 percent are possible for a 0.25-micron technology using multiple supply voltages and about 32 percent using a single external supply voltage, they said.
Also at VDAT, Bedanta Choudhury of STMicroelectronics India juxtaposed design-for-manufacturability (DFM) needs against design-specific requirements involved in creating standard cells, the basic building blocks of analog and digital circuits. An intelligent compromise can be made by fusing design expertise with manufacturing-process expertise, he said. The paper discussed ways to make CAD and design tools DFM-intelligent to achieve higher semiconductor reliability. It said that while leading EDA companies have launched some promising tools in the market, there is much more scope for R&D in DFM-smart EDA.
Engineers at Texas Instruments India presented a method for achieving predictability in crosstalk noise analysis and closure by identifying the real- and root-cause noise problems needing to be fixed so that new violations are not discovered after repair. Their method aims at reducing pessimism in the analysis by using data arrival times and "slack" information, and draws a relationship between the timing slack and glitch criticality. The TI team discussed gaps in hierarchical crosstalk analysis methods and presented a flow to fill those gaps.
Another paper described a methodology based on a parameterized analog cell library to automate analog design. One paper found that the results from testing both the cores and the interconnects between them in systems-on-chip were better than when the cores and interconnects were considered separately.
"The VDAT program is meant to promote research and development in all areas of VLSI in India and is a reflection of the excellent work being carried out in the area of VLSI in Indian industries, research organizations and academic institutions," said C.P. Ravikumar of Texas Instruments India, the head of the VDAT program committee.
To bring VLSI professionals on one platform.
Establish relations with other associations.
The intention of the MoU is to strengthen the bonds between VTU and the semiconductor industries in India. VTU represents a conglomeration of over 250 engineering colleges and gives the semiconductor industry a great opportunity to get involved with the academia, provide inputs in improving the curriculum, delivering seminars, teaching courses, and so on.
The third VTU-VSI-ISA Confluence meeting was held at Hubli on October 13, 2006.
The fourth VTU-VSI-ISA Confluence meeting at RVCE, Bangalore on February 28, 2007.
The proceedings of all the Confluence meetings are available as softcopy. Write to email@example.com for details
VLSI/Embedded Systems Curriculum
13th April 2007:
|| On June 27, 2005, the Indian Semiconductor Association (ISA), the Visvesvaraya Technical University (VTU), and the VLSI Society of India (VSI) jointly entered a Memorandum of Agreement (MoU) starting June 2005 with the goal of strengthening the industry-academia interaction.
A panel discussion was held at Global Institute of Technology, Bangalore, on the topic of VLSI/Embedded Systems Curriculum.
It was moderated by C.P. Ravikumar (Texas Instruments, India). The participants were S. Kartik, Analog Devices (India), Gopal Krishna (Maxim, India), and D. Madheswaran, Wipro.
Fourth VTU-VSI-ISA Confluence meeting
28th February 2007:
VLSI Society of India
Supported by R.V. College of Engineering
, Bangalore, and India Semiconductor Association
Venue: Main Auditorium, RV College Campus, Mysore Road, Bangalore
Anuradha Srinivasan, Intel India; Dr. C.P. Ravikumar, Texas Instruments India; Madhav Chikodikar, Synplicity; Nisha P.K., Texas Instruments India; Arun Pradeep, NXP Semiconductors India, and Razak Mohammed Ali, Alterra Semiconductor India
A Profession in Semiconductor Industry – What “IT” is and what “IT” is not.
C.P. Ravikumar, Texas Instruments India
N.S. Murty, NXP Semiconductors India; A. Vasudevan, Wipro Technologies; Ram Jonnavithula, Texas Instruments India; V. Veerappan, Tessolve India
Third VTU-VSI-ISA Confluence meeting
13th October 2006:
B.V.Bhoomaraddi College of Engineering and Technology (BVBCET), Hubli
C-lite Seminar hall, BVB Cmpus, Hubli-580 031
Report by Anil Nandi, BVBCET, Hubli
The third VTU-VSI-ISA confluence meeting was held on October 13, 2006 at BVB College of Engineering and Technology, Hubli. This is an event in the series of such programs being held under the aegis of the Memorandum of Understanding between the Visweswaraya Technical University (VTU), India Semiconductor Association (ISA) and VLSI Society of India (VSI). The intention of such meetings is to promote the subject of VLSI and semiconductors among the academic community of the VTU and help the students and faculty of the M.Tech - VLSI and Embedded Systems stream to gain knowledge of industrial practices.
The event was attended by 200 participants including faculty and students from various colleges in the state, including RVCE Bangalore, SJCE Mysore, BEC Bagalkot, VTU Belgaum, BIET Davanagere, GIT Balgaum, BVBCET Hubli and many Engineering Colleges in the vicinity of Hubli. Seven speakers from the VLSI industry made tutorial presentations at the meeting.
The Principal of BVBCET, Hubli, Dr. Ashok Shettar, welcomed the gathering. Dr.S.Mahant-Shetti, CEO, KarMic, Manipal, inaugurated the confluence. He spoke about the need for quality education. He emphasized that modern education needs planning, execution and measurement. He highlighted the method of training provided at KarMic, Manipal.
We thank the efforts of Prof. B.V. Desai of BVB College of Engineering, Hubli in organizing the event. We also thank Poornima Shenoy of ISA for her help.
Mr. Arun Pradeep, NXP Semiconductors, Bangalore, spoke on the topic of Advent of new technologies in mobile multimedia and communications. He introduced some new trends such as “Push to talk” on Cellular phones, TV on Mobile, Mobile with Near Field Communications, Mobile for people hard of hearing, Location based Services and Mobile Content management.
Mr. Gururaj Badiger, NXP Semiconductors, Bangalore, spoke on the topic of Embedded systems- A case study on Digital TV. He provided an introduction to Analog TV and Transmission Standards, Digital Transmission and Reception, System Architecture, Software Architecture, Debugging.
Mr. P.Radhakrishnan, Open-Silicon, Bangalore, spoke on the topic of SOC/ASIC design flow. His tutorial covered the concepts of ASICs, ASIC Design Flow, Front end, Backend, Synthesis, Floor plan, Clock Tree, Routing, Static Timing Analysis, and Packaging.
Mr. Razzak Mohd. Ali, Manager, Altera systems, Bangalore, spoke on DSP System Design Using FPGAs. The talk covered the role of FPGAs in DSP applications, DSP Features in FPGAs, FPGA Tools for DSP Design, DSP Design Flow, and Case Studies.
Mr. Girish Baliga, Application Manager, CG-Corel Bangalore, spoke on the topic of Fast & Flexible Embedded Processing using Xilinx FPGAs. Mr. Prabhat Agarwal, Manager, Sankalp semiconductor, Hubli spoke on the topic of High speed chip interface. He highlighted on the necessity of high speed chip interface/IO, IO Functions, Commonly known Interface Standards, IO Design Challenges, Latest Trends in High Speed, LVDS – Specification/ Architecture and its future.
Mr. Kamal Aggarwal, Intel Technology India Pvt. Ltd spoke on the topic The Current Buzzword in Semiconductor Industry Optimization and Efficiency. He highlighted on Custom Design Flow, Challenges faced by the Industry, and how automation can be a Savior and Challenger.
VTU meets with ISA, VSI
April 28, 2006:
The Visvesvaraya Technological University-Belgaum recently met with the VLSI Society of India
(VSI) and the India Semiconductor Association
(ISA), providing a means for faculty members, students and the semiconductor industry to come together.
VTU had earlier entered into a memorandum of understanding (MoU) with VSI and ISA to strengthen its link with India's semiconductor industry.
At the meeting VTU Vice-Chancellor Dr. K Balaveera Reddy shared that the university is made up of 121 engineering colleges. This gives the semiconductor industry a great opportunity to get involved with academia, providing inputs in improving the curriculum, delivering seminars, and teaching courses.
The meeting is the second activity in the events lined-up in the MoU. According to the organizers, the meeting was arranged to provide updates in the semiconductor industry to M.Tech students. Around 75 M.Tech VLSI students from selected institutions participated in the meeting and presented papers on various topics.
Several industry experts also presented technical papers. Dharmaraya M Nedalgi of Philips Semiconductor presented a paper on "Issues in IO Cell Design" that discussed the challenges in designing an IO cell, and covered areas such as noise margin, multiple supply domains, load, different signalling, supply bounce, hot-plug design, high voltage signalling, process technology, latch-up, electro migration, ESD and other related issues.
Razak Mohmmad Ali from Altera Semiconductor India presented a paper on how to use FPGA devices to build embedded systems and embedded system designs.
Gap between students' capabilities and industry requirements
Speaking to EE Times India after the event, Dr. M.S. Shivakumar, VTU's Registrar, said that the expected outcome of inviting industry inputs to the curriculum was to upgrade the university's syllabus for VLSI and embedded systems design, and reduce the gap between students' capabilities and the requirements of India's semiconductor industry.
"Industry has emphasised the importance of exposing students to recent tools for VLSI design that are used in industry," said Shivakumar. "Traditionally, universities have been resorting to preliminary freeware tools that provide a very basic exposure to students, due to the expenses involved in acquiring the complete tool sets. We are now making the transition to using actual tool sets that VLSI design engineers use in industry.
" One of the key issues involved in equipping the university with the latest tool sets is their cost. "We have requested the industry to make tools more affordable for us. EDA tool companies like Cadence, Synopsis, and Mentor have all made their tools available to us at a very nominal cost. So have Intel and Sun Microsystems with regard to the hardware for the laboratory, and Microsoft for the systems software environment," said Shivakumar.
The definition of projects too has undergone a change to relate it more closely to what students may encounter in actual work in industry. "A list of projects for VLSI and embedded systems design has been defined by the industry members of the ISA. Their expectation is to have an actual product developed as an outcome of the project effort," Shivakumar explained.
"The projects will put students through the entire design and development life cycle, spanning design, synthesis and testing. Students will carry out project work under supervision by a faculty member from the college who will closely monitor the quality of project work."
According to Shivakumar, VTU interacts with industry on critical aspects such as syllabus design, industry guidance for establishing fully equipped laboratories at the university, and placement of students in industry.
Krishnan Sivaramakrishnan, EE Times India
Presentations at the 2nd Confluence meeting
Challenges in Analog Design
- Kaushal Jha, Analog Devices, India
Biasing technique, stability analysis, noise analysis, mismatch analysis, substrate noise in mixed signal design
Challenges in IO Design
- Dharmaray M. Nedalgi, Philips Semiconductors
Issues in IO Cell Design
Embedded System Design using FPGA
- Razak Mohmmad Ali, Altera Semiconductors India
How to use FPGA devices to build embedded systems - includes demo
Challenges in Low Power Design
- Lakshminarayanan Venkatachalam and Umapathy Jayaraman, Intel India
Student Paper Presentations
Wakeup Fresh Alarm
K. Subashith, Santosh Gokak, Apurva Shukla, Colin Rebello, Shweta Shanbhag, Shreyaswini K. and Vijaykumar Thombare Smart Seeder
Sumit J Bhat, Vijaykumar PJ, Nusaiba CA, Vijayanand MJ, Sainath D Patil, Shashikala SG and Mahantesh KT Fun with Faces
Kiriti Kakkar, Lingraj Aras, Manoj Kumar, Rayagond Kaakatunar, Sankar Ghosh, Shashishekhar Patil and Shridhar Moorkhandi
Blind, but not Color Blind
Archana Shetty, Madhuri Chowdhary, Malesh S Mugalakhod, Mallikarjun A Biradar, Poornima M Kadakol, Prashant Wilson Crasta P, Rauf S, Shwetha Shetty and Sravani Das B
Sudoku - Numbers that outnumber You!
Amruta G Pawar, Sandeep Nayak, Anoosha Shetty, Seema Hegde, Narayan S Mahipati, Shashikala V Pawar, Prashant Kulkarni, Shubhalakshmi M and Ravi S Siddanath
Industry-Academic Confluence Meeting at Bangalore
Announcement A brief report
Feb 24, 2006, Bangalore:
The VLSI Society of India signed an MoU with the Visvesvaraya Technological University (headquartered at Belgaum, Karnataka) and the India Semiconductor Association in August 2005 in order to spread and improve the quality of VLSI Education. Under the aegis of this MoU, colleges that offer M.Tech programs in VLSI Design and Embedded Systems have been identified as centers where champions from the industry will work in close cooperation with faculty champions to improve the quality of M.Tech programs.
The complete list of the colleges includes:
Gnanasangama Campus, VTU, Belgaum
BMS College, Bangalore
UTL Extension Centre, Bangalore
BVB Engineering College, Hubli
PDA College of Engineering, Gulbarga
RV College of Engineering, Bangalore
Dayananda Sagar College of Engineering
Industries that have come forward to interact with these colleges include Altera, Intel, Texas Instruments, ST Microelectronics, AMD, and many others. A confluence meeting, which brought together all the M.Tech students, the faculty, and the industry champions, was held at BMS College, Bangalore, on February 24, 2006. The conference was inaugurated by Prof. Balaveera Reddy, Vice Chancellor of VTU, who emphasized the importance of the MoU and the confluence meeting. He felt that the MoU between VTU, VSI, and ISA is very special because it involves a large number of industries and has the potential to provide the much-needed academia-industry interaction. He called upon ISA and VSI to contemplate an M.Tech program in VLSI Design that can be offered jointly by the three bodies. Poornima Shenoy, the President of ISA, explained the background of the MoU and the activities that can be planned under its umbrella. She felt that in addition to curriculum improvement in technical subjects, there is a need to emphasize on soft skills which are necessary for a professional to succeed in the area of semiconductors. Dr C.P. Ravikumar, secretary of VSI, felt that this meeting can set into motion a series of events that the colleges can organize over the year to keep their M.Tech programs vibrant. He announced the next event at Gnanasagama Campus, Belgaum, on April 28. He announced an essay writing competition WHY I Chose To Become A VLSI Professional sponsored by the VLSI Society of India for the M.Tech students of VTU specializing in VLSI/Embedded Systems. The details of the essay competition
(PDF) have been announced on the VSI website. Prof. K. Jayaraman and Prof. V. Sreedhar of VTU thanked everyone who have helped in organizing the meeting.
The purpose of the meeting was to provide exposure of the VLSI industry in India to the M.Tech students. A number of presentations were made by several industries towards this goal. A brochure containing salient details of many local industries was released during the conference. Dr S.S. Mahant-Shetty of Karmic, Manipal, spoke about the topic of student projects in the area of VLSI/Microelectronics. He explained the two theories, “Theory Y” and “Theory X” first popularized by Maslow McGregor. The Theory Y postulates that The expenditure of physical and mental effort in work is as natural as play or rest. The second theory postulates that “The average human being has an inherent dislike of work and will avoid it if he can. Because of their dislike for work, most people must be controlled and threatened before they will work hard enough.” Which one of these must be applied to student projects in microelectronics? Dr Mahant-Shetti gave examples of how the use of “Theory Y” has led to successes in student workshops held at Manipal. For example, the CLDW 2005
held under the aegis of VLSI Society of India during the summer of 2005 saw the participation of about 40 students and faculty. One of the projects completed during this workshop has since been presented at VDAT 2005
and published as a regular paper in VSI VISION (December 2005). He gave tips on making projects successful through the deployment of “Theory Y.”
As part of the “industry exposure” campaign, Dr C. P. Ravikumar spoke about the ongoing work at Texas Instruments India and described the various products and market segments where Texas Instruments operates. He spoke about the DSP related products, wireless chipsets, ASICs, and high performance Analog products being designed at TI India. Dr H.V. Ananda of Synplicity spoke about the EDA industry in general and the kind of skill sets required to work in the EDA industry. He emphasized that when one works in the EDA industry, an engineer will most certainly use 100% of all the knowledge gathered during the four years of the engineering curriculum. He also explained the ongoing product development work at Synplicity Bangalore. Sanjay Bansal spoke about the work on embedded systems at Philips Semiconductors, India. He explained how embedded systems touch every aspect of human life today, from the morning wakeup call and throughout the day. Biswadeep Chatterjee of Intel spoke about the implementation challenges offered by sub-100 nanometer design technology. He opened up several avenues where student projects are possible, such as a power routing algorithm for system-on-chip designs, handling of signal integrity problems such as crosstalk and IR drop. Saj Kapoor of Analog Devices exposed the students to the challenges faced in designing DSP chips. He explained how full custom design may be necessary when high performance and low power are necessary, and how cell-based design is necessary when time-to-market is critical. Mukund Srinivasan of Wipro spoke about the design services offered by Wipro in the areas of VLSII and Embedded system design. With the acquiring of New Logic by Wipro, the latter has become a major IP provider in IEEE 1394. He explained how the design services offered by Wipro have steadily moved up the value chain.
The day ended with discussions among the industrial participants, students, and faculty. The next confluence meeting will be held at Gnanasangama Campus, Belgaum, on April 21, 2006.
Foils of the "Industry Exposure" campaign presentations are available here:
Some VLSI Related Books...
|| VSI Mission
Provide impetus on HR development.
Bring out quality publications.
There was a suggestion for the VSI website to display VLSI-related books costing less than Rs 250/-, specially for the students. We have tried listing a few. You may also suggest
other books to include on this page.
Multi-core Embedded Systems
VLSI for Wireless Communication - Bosco H. Leung
Wireless Communication Systems : Advanced Techniques for Signal Reception - Xiaodong Wang, H. Vincent Poor
A VHDL Primer - J. Bhasker
Digital Integrated Circuits - Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic
Intel Microprocessors 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium, Pentium Pro Processor,
Pentium II, Pentium III, and Pentium IV : Architecture, Programming, and Interfacing - Barry B. Brey
The 8051 Microcontrollers & Embedded Systems - Muhammad Ali Mazidi, Janice Gillispie Mazidi
Verilog HDL - Samir Palnitkar
Basic VLSI Design - Pucknell Douglas A., Eshraghian Kamran
Edited by: Georgios Kornaros (TEI of Crete, Greece) Details
... PDF 661 KB
The book begins with an overview of the evolution of multiprocessor architectures for embedded applications and discusses techniques for autonomous power management of system-level parameters. It addresses the use of existing open-source (and free) tools originating from several application domains - such as traffic modeling, graph theory, parallel computing and network simulation. In addition, the authors cover other important topics associated with multi-core embedded systems.
As part of a continuing feature on Embedded.com, the editors have been working with publishers of engineering and programming books, selecting material from recent embedded hardware and software titles for posting on the site. As a part of our Embedded Book department, collected here are some of the selections posted so far, with new ones added each week as they become available...
To bring VLSI professionals on one platform.
Establish relations with other associations.
VLSI Education Award
16 years. He started the LinAsic design centre in Texas Instruments India, Bangalore in 1988-89, the first commercial chip design activity in India.
||During VDAT2006, August 9-12, 2006 at Goa, VSI honored Dr.S.S. Mahant-Shetti, KarMic, Manipal with the VLSI Education Award for his significant contributions to the field of VLSI Education through the two-week Custom LSI Workshops he conducted at Manipal (2005) and Goa (2006).
Dr. Mahant-Shetti received the B. Tech (Hons) in Electrical Engineering from the Indian Institute of Technology in Bombay, India in 1972. He earned Sc.M and Ph.D. degrees from Electrical Sciences from Brown University in 1975 and 1977 respectively. He worked in Astro-Med Division of Atlan Tol Industries , Warwick, RI. for five years. He joined the research laboratories at Texas Instruments, Dallas and worked for
His Professional achievements include:
|| Senior Member of the Technical Staff in 1987
Distinguished Member of Technical Staff in 1998.
Technical program committee of the International Conference of Microelectronic Test Structures in 1988
Publication of over 35 papers
67 issued patents
Some of Mahant's Key Technical Contributions:
Long Range Opportunity -Silicon Transform Cameras, SPICE Model Verification for digital circuits, Definition of 0.6µm and 0.5µm technologies, Automatic testchip design, Several significant chip designs. As part of TestChip Technologies/Covalar, he started Karnataka Microelectronic (KarMic) Training / Design Centres in Manipal, Karnataka, India in 1999. KarMic is involved in Analog, mixed signal designs and boasts a 98.2% retention.
Recognition of Volunteer Service
VLSI Society of India recognized the significant contributions made by Yashdeep Mahajani towards the construction and maintenance of Website for VDAT and VSI during 2001 – June 2006.
Details VSI Vision Vol-2, Iss.-1, Aug-06 pdf.
Shanti Swarup Bhatnagar Prize 2005
||Dr. Thulasiraman receives IEEE CAS Technical Achievement Award 2006
Dr. Krishnaiyan Thulasiraman has received the 2006 Technical Achievement Award from the IEEE Circuits and Systems Society. VLSI Society of India congratulates Prof. Thulasiraman on this significant recognition, which has been given for sustained and outstanding technical contributions for nearly four decades to graph theoretic foundations of circuits, systems and computing emphasizing theoretical and algorithmic aspects and bridging theory and practice in diverse areas of applications ranging from classical circuit theory to modern areas such as VLSI physical design, VLSI testing, fault tolerance in WDM optical networks, etc. For sustained leadership efforts in promoting graph theory based research through research publications, text books, monographs and CAS society technical committee/editorial/conference activities.
||VSI congratulates Prof. V. Ramgopal Rao, Dept. of Electrical Engineering, IIT Bombay, who has been selected for the prestigious Shanti Swarup Bhatnagar Prize 2005 of the Council of Scientific & Industrial Research (CSIR),Government of India in Engineering Sciences. This award is given to him in recognition of his outstanding research contributions in the area of Electron Devices and Nanoelectronics. The award was presented by the Prime Minister Dr. Manmohan Singh on September 28, 2005 in Delhi.
Prof. Rao is a Member of the “Working Group on Nanotechnology”, Ministry of Communication & Information Technology, Government of India. He had also received the ‘Swarnajayanti Fellowship’ Award in 2003-04. He is currently serving as an Editor for the IEEE Transactions on Electron Devices for the MOS Devices and Technology area, is a Distinguished Lecturer, IEEE Electron Devices Society, and is a
Fellow of The Institution of Electronics and Telecommunication Engineers. Prof. Rao has guided over 75 post-graduate/dual degree/Ph.D. theses in the area of microelectronics/nanoelectronics till date at IIT Bombay.
He has to his credit over 150 research publications in international journals and conference proceedings and holds two patents, including a US patent on SRAM cell. The S.S. Bhatnagar award given to Prof. Ramgopal Rao is in recognition of his significant contributions to the area of Silicon CMOS devices and the device optimization in the sub 100 nm regime. The technologies proposed by him are helpful in reducing the cost of the ‘System on Chip’ technologies, as it offers a way to realize the analog/RF functions using the standard silicon CMOS platform.
His current areas of interest are Nanoelectronics, Circuit and System Design Considerations for sub 45nm node CMOS Technologies and Bio-MEMS. He works closely with various semiconductor industries in India and abroad, and has many ongoing sponsored projects from industries and government funding agencies.
Appeared in VSI Vision Volume 1, Issue 1: August 2005 pdf.
Life-time Achievement Award for Prof. Vishwani Agrawal
Jan 03, 2006; Hyderabad:
At the 19th International Conference on VLSI Design, Hyderabad, the VLSI Society of India and the organizing committee of the conference presented the life-time achievement award for Prof. Vishwani Agrawal of Auburn University. The award was presented by Dr Bobby Mitra, President, VSI at the awards ceremony held as part of the conference.
||Vishwani Agrawal is known to the VLSI community of India as the founder of the VLSI Design Conference and as a “Guru” in the area of VLSI Test. When receiving the award, Dr Agrawal thanked the committee and the VSI and paid tribute to his own teachers from whom he had learnt. The life-time achievement award is given to individuals who have made exceptional contributions to the area of VLSI.
In the past, Prof. Sudhakar Reddy of the University of Iowa and Prof. C.L. Liu of the University of Illinois, Urbana Champaign, have been conferred the award.
VSI congratulates Prof. Vishwani Agrawal and takes pride in placing on record his many achievements.
James J. Danaher Professor of Electrical and Computer Engineering at Auburn University, Alabama
Over 30 years of industry & university experience
Bell Labs, Murray Hill, NJ;
Rutgers University, New Brunswick, NJ;
TRW, Redondo Beach, CA; IIT, Delhi, India;
EG&G, Albuquerque, NM;
ATI, Champaign, IL.
Areas of Interest -VLSI testing, low-power design, and microwave antennas
BE degree from the University of Roorkee, Roorkee, India, in 1964
ME degree from the Indian Institute of Science, Bangalore, India, in 1966
PhD degree in electrical engineering from the University of Illinois at Urbana-Champaign, in 1971
Published over 250 papers
Coauthored five books
Thirteen United States patents.
Founder and Editor-in-Chief (1990-) of the Journal of Electronic Testing: Theory and Applications
Past Editor-in-Chief (1985-87) of the IEEE Design & Test of Computers magazine
Founder and Consulting Editor of the Frontiers in Electronic Testing Book Series of Kluwer Academic Publishers, Boston
He is a co-founder of the International Conference on VLSI Design,and the International Symposium on VLSI Design and Test,
held annually in India.
Served on numerous conference committees and is a frequently invited speaker (Plenary talks at ITC 1998, ATS 2000)
Served on the Board of Governors of the IEEE Computer Society (1989, 1990)
Chaired the Fellow Selection Committee (1994)
Awards and Recognitions
Seven Best Paper Awards and one Honorable Mention Paper Award
Harry H. Goode Memorial Award of the IEEE Computer Society for "innovative contributions to the field of electronic testing"
Distinguished Alumnus Award of the University of Illinois at Urbana-Champaign, "in recognition of his outstanding contributions
in design and test of VLSI systems"
Fellow of IETE-India
Fellow of the IEEE (elected in 1986)
Fellow of the ACM (elected in 2003)
Served on Advisory Boards of the ECE Departments of the University of Illinois, New Jersey Institute of Technology,
and the City College of the CityCollege of New York