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VLSI Design And Test Symposium
To promote applications and research related to all aspects of VLSI in India

About VDAT

VDAT History

Related Info

Guidelines to authors

VDAT2008 an Overview

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VDAT 2008

VDAT2008, the 12^th IEEE VLSI Design And Test Symposium was conducted during July 23-26, 2008, at the Wipro Campus, Electronics city, Bangalore.

The four-day event included Full-day tutorials, keynote and invited talks, and panel discussions on topics related to VLSI design. The Technical papers and Embedded Tutorials covered varied subjects on Analog design, Biomedical applications, Digital design, Interconnect, Low-power, Memory, RF Design, Testing, Timing, and Verification.

Visit VDAT2008 webpage for details.

Symposium Committee
General Chair
C.P.Ravikumar, Texas Instruments India
Technical Program Chair
Shabbir Batterywala, Synopsys, India
Tutorial Chair
Rubin Parekhji, Texas Instruments India
Finance Chair
S.R.Gopal Naidu, TI India
Local organizination Chair
Santhosh Kumar Madathil, Wipro Tech.
Registration Chair
C.R.Venugopal, SJCE, Mysore
Sponsorship Chair
N.S. Murty, NXP Semiconductors
Fellowship Chair
P.P.Das, Interra Systems India

Tech. Program Committee
Details

Sponsored by
VLSI Society of India

Industry Sponsors
Wipro Technologies
Texas Instruments India
NXP Semiconductors
Synopsys India
Arm Embedded Technologies
Corporate Sponsor
Intel India
In co-operation with
IEEE-CAS Bangalore Chapter
Supported by
Microsoft's CMT VDAT2008 Sponsors

Goals of VDAT Symposium

The idea behind VDAT or the VLSI Design And Test Symposium is to promote Research and Development on all aspects of VLSI in India. This symposium is a forum for free discussion on hot and emerging topics on VLSI and the related for VLSI professionals from India and abroad.

VDAT began in 1998 as a workshop with about 30 participants at Chennai. With the participation growing steadily each year, from the year 2005, VDAT has acquired the status of a Symposium. The VLSI Industry in India and academic community working in the area of VLSI have provided immense support to the symposium. The symposium runs for four days, and is conducted during August each year, with participation from accross the world.

VDAT is organized by the VLSI Society of India, with support and sponsorship from leading institues and the industy.

Technical papers

Original and unpublished works are invited which undergo a blind review process by the peers in the field. Authors of accepted papers will be required to submit full papers and presentation foils. Final submissions are made available as proceedings of the symposium in both CD and hardcopy format. For a list of previous VDAT proceedings available, visit VSI publications.

Tutorials

The first day of the symposium is devoted to Tutorials conducted by experts in the field. Three separate tutorials on diverse topics run concurrently, which can be attended separately.

VLSI Education Day

The second day of the symposium is observed as VLSI Education Day with an intention to bring together VLSI professionals in academia and the industry. VLSI Education Day includes:

Student projects

Keynote speeches from eminent personalities

Panel discussion on topics related to VLSI Education in India

Invited talks from VLSI Professionals

Short paper presentations from Indian Colleges

The third and fourth day of the event are devoted to presentations of the accepted technical papers, keynote speeches and panel discussions. From the year 2006, VDAT has introduced the Research Scholars' Forum. Researh scholars can submit their Ph.D. theses which are briefly reviewed by the committee. The overview of selected theses can be presented by the authors during the session attended by the Experts to provide feedback.

Fellowship

Fellowships are made available to teachers, students and research scholars from educational institutions to attend VDAT. Applicants should submit the Felowship form before the set date. The selected list by the Fellowship committee will be displayed on our website, besides being intimated by mail. Fellows must first register with the fellow category tariff under registration details. In the event of non-selection, the balance amount should be sent to attend the event. Details under fellowship.

Registration

Any one interested in the field of VLSI can register and attend the event. At least one author of each selected paper must register and present the paper. Please refer Registration details.

VDAT Event History

VDAT began as a small workshop in the year 1998. In 2005, it acquired the status of a Symposium.
The proceedings of VDAT are published in both hard and softcopy format. Visit VSI Publications for details on proceedings and Photo Gallery for images of past VDAT and VSI events.
More details on past VDAT Workshops and Symposium.

Event Place Date Participants

1st VDAT Workshops Chennai Jan 7, 1998 30

2nd VDAT Workshops Habitat World, New Delhi August 6-7, 1998 70

3rd VDAT Workshops New Delhi August 20-21, 1999 120

4th VDAT Workshops New Delhi August 25-27, 2000 150

5th VDAT Workshops Bangalore August 16-18, 2001 200

6th VDAT Workshops Bangalore August 29-31, 2002 320

7th VDAT Workshops Bangalore August 28-30, 2003 300

8th VDAT Workshops Infosys Leadership Institute, Mysore August 26-28, 2004 250

9th VDAT Symposium Wipro Learning Center, Bangalore August 10-13, 2005 300

10th VDAT Symposium International Centre, Goa August 9-12, 2006 220

11th VDAT Symposium Saha Inst of Nuclear Physics, Kolkata August 8-11, 2007 250

12th VDAT Symposium Wipro Campus, Bangalore July 23-26, 2008 200

VDAT Mailing Group

A mailing group is setup at http://groups.yahoo.com/group/vdat to provide information about the VLSI Design and Test Symposium held in India every August. In addition, information about other similar events taking place in India or abroad is also disseminated through this mailing list.

You may use vdat@yahoogroups.com to publicize events related to VLSI Design/EDA/Test that take place in and around India. You can also use this address to discuss/debate issues related to VLSI in India. The list owner of the VDAT mailing group may be contacted at: vdat-owner@yahoogroups.com.

To subscribe, you may send a mail to vdat-subscribe@yahoogroups.com

To unsubscribe, send a mail to vdat-unsubscribe@yahoogroups.com

You will receive a confirmation mail, to be acknowledged within a week to subscribe/ unsubscribe.

Become a VDAT Mailing Group member to keep yourselves updated on forthcoming events.

Faculty Page

http://groups.yahoo.com/group/vlsi-faculty-india

This is meant only for Indian faculty in the area of VLSI/semiconductors/microelectronics. Anyone who wishes to subscribe must send a note from their official e-mail ID with details such as: Name, Designation and Affiliation to

vlsi-faculty-india-subscribe@yahoogroups.com Or visit the site and click Join This Group

Feedback: Please use the feedback form for your queries.

Related sites
VLSI Related sites

International Conference on VLSI Design and Embedded Systems

Disclaimer

Though all efforts have been made to ensure the accuracy and currency of the content on this Portal, the VLSI Design and Test (VDAT) Symposium Program Committee and the associated web-masters accept no responsibility in relation to the accuracy, completeness, usefulness or otherwise, of the contents. Users are advised to verify/check any information with the relevant source(s), and to obtain any appropriate professional advice before acting on the information provided in the website. In no event will the VDAT Symposium Program Committee and/or the associate web-master be liable for any expense, loss or damage including, without limitation, indirect or consequential loss or damage, or any expense, loss or damage whatsoever arising from use, or loss of use, of data, arising out of or in connection with the use of this Portal.

Linking Policy

At many places on this website, you shall find links to other websites/portals placed for your convenience. We are not responsible for the contents and reliability of the linked websites and do not necessarily endorse the views expressed in them. Mere presence of the link or its listing on this Portal should not be assumed as endorsement of any kind. We can not guarantee that these links will work all the time and we have no control over availability of linked pages.

We do not object to you linking directly to the information that is hosted on this website with no prior permission, but would like you to inform us about links provided to this website, to keep you informed on changes or updates. Also, we do not permit our pages to be loaded into frames on your site. This website must load into a newly opened browser Window of the user.

Guidelines to authors

The submissions should represent original contribution and should not have been submitted to other forums.

It is important that abstracts bring out the contribution and novelty of the paper.

Students must note that reusing material from published work is incorrect and amounts to violation of copyright.

Survey papers are not acceptable.

Submitting authors must become members of the VDAT mailing list, where updates are sent.

Authors must upload their submissions at the specified website, and must not send it through mail.

Submissions will undergo blind review – the authors must not include their names or affiliations.

Notification

All the submitting authors are notified on the status of acceptance via mail, and the reviews are displayed on the relevant website, to aid the authors of accepted papers to improvize final submission.

Page limit

The accepted papers are published in the hardcopy of proceedings, and also distributed as softcopy along with their slides. The papers are categorized as Full papers/Embedded Tutorials and Short Papers. Full papers get 10 pages in the hardcopy and Short papers 8 pages. As the paper size of the VDAT proceedings are smaller than letter size, follow the guidelines to format page layout.

The set page limit for both category includes figures, text, references etc.,

If the authors notice that they are exceeding the page limit set by the committee, they must contact the Publications Chair for approval. The publications chair has the authority to approve one extra page. Authors have the option of buying at most two extra pages by paying Rs. 1000/- per page. Send the DD to Finance Chair; and make the draft payable to “VLSI Design and Test Symposium (year as applicable).”

One or more of the authors must register as a participant and present the paper.

Formatting

Papers that do not comply with these guidelines will not be included in the hardcopy proceedings.

Papers must be submitted in DOC format using Microsoft Word. No other formats are acceptable.

Do not include color photographs or graphics.

Figures must be of high resolution and must not have gray background.

Importing bitmap images in Microsoft Word will not be acceptable.

Authors must not use any material (figures and/or text) from the Internet or other sources without acknowledgement.

The authors must output hardcopy of their manuscript and ensure that all the figures are legible and also output PDF to verify the figures and tables show up before sending. PDF is used for the softcopy.

Note

Please visit for further details on Page formatting DOC and PPT foils, and to download template file.

VDAT2008

July 23-26, 2008
Wipro Campus
Electronics City
Hosur Road
Bangalore, India

VDAT2008
Accepted Papers
Technical Program PDF
Invited Talks
Tutorials 23 July
Fellowship
Registration
Venue
Hotels at Bangalore
Accommodation
Symposium Committee

Full-day tutorials on July 23, 2008 and the Symposium during July 24-26, 2008 require separate registration. Please refer to related details.

Last Dates

Paper submission: March 15, 2008
Tutorial submission: March 15, 2008
Notification of acceptance: April 25, 2008
Camera-ready submission: June 2, 2008
Fellowship Application: June 10, 2007
Final presentation: June 25, 2008
Program
Symposium Dates: July 23-26, 2008
Full-day Tutorials: July 23, 2008
VLSI Education Day: July 24, 2008
Technical papers: July 25-26, 2008

Technical Sessions
Analog, Design Implementation, Low power, Memory, Technology, Testing, Timing, Verification

Sponsors
Organized by
VLSI Society of India
Industry Sponsors
Texas Instruments India, Wipro Technologies, NXP Semiconductors, Synopsys India, Arm Embedded Technologies
Corporate Sponsor
Intel India
In cooperation with
IEEE-CAS Bangalore Chapter

Technical Program

July 23: Full-day Tutorials
Tutorial – I
RF Design and Test
RFIC Design and Testing for Wireless Communications
Vishwani Agrawal and Foster Dai, (Auburn University)
Tutorial – II
Low Power Design
SoC Power Management Architecture Design and Verification
Dr. Bhanu Kapoor (Mimasic), Shankar Hemmady (Synopsys), and Sandeep Aggarwal (TI)
Ultra Low-Power Processors for Embedded Systems
Atul Lele (Texas Instruments) and Gurjit Singh Gill (Gill Instruments)
Tutorial – III
Design Verification Methodologies
Holistic Verification: Myth or The Magic Bullet?
Pradip Thaker, Analog Devices
Foundations of Design Verification- Formal and Functional Approaches
Ansuman Banerjee; Kausik Datta; and Amit Roy (Interra Systems India Pvt. Ltd.)
Design Verification using Static Checker and Verification of Clock-domain Crossing
Kaushik De, Synopsys
July 24: VLSI Education Day
Panel discussion
Growing the Right Talent for a Growing Semiconductor Industry
Technical papers, Embedded Tutorials
July 25-26: Technical presentations
Technical papers; panel discussion; Invited Talks; Keynote addresses and a Banquet talk; Embedded Tutorials

Symposium Highlights

Keynote talk: VLSI Education Day
Teaching and Research in Microelctronics at IIT Bombay - A view from Lake Powai
Arun N.Chandorkar, IIT Bombay
Keynote talk: July 25 - Enabling Systems on a Chip to Test Themselves
Jacob A. Abraham, Univ. of Texas, Austin
Keynote talk: July 25 - Electronic Design Evolution in India and its Impact on Semiconductor Design
Sudip Nandy, Wipro Technologies
Keynote talk: July 26 - Physical Design EDA Challenges for 32nm and Beyond
Mysore Sriram, Intel
Invited Talks
Special session: Biomedical Applications
Innovation Opportunities in Biomedical Electronics
Shekar Rao, Texas Instruments Inc.
Connected Healthcare
Dinesh Bhatia, Univ. of Texas, Dallas
Moving Event Localization using Multihop Cellular Sensor Networks
Uday B. Desai, IIT Bombay
Low Power Verification - overcoming the challenges
Srikanth Jadcherla, Synopsys Inc.
System Verilog for VLSI design - prospects and challenges
Dr.N.S.Murty, NXP Semiconductors
Design Methodology for a 2.5GHz Native Quad Core x86 Processor
Prasad Kuppa, AMD
Presentation by ARM Embedded Technologies
Jayanta Lahiri, ARM Embedded Technologies
Embedded Tutorials, Research Scholars’ Forum