| Tutorial – T1 | Full-day Tutorial (6 hrs) |
| Open Source Embedded System Development using Beagleboard Syed Khasim (Texas Instruments India) |
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| Tutorial – T2 | Full-day Tutorial (6 hrs) |
| Compact Modeling and PDK’s Madabusi Govindarajan, Tamilmani Ethirajan, Abhisek Dixit, and Josef Watts (IBM) |
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| Tutorial – T3 | (Part 1) |
| Test Cost Reduction Techniques, Current Practices, Challenges and Impact Sarveswara Tammali (Texas Instruments India) |
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| (Part 2) | |
| Test Power Reduction Techniques: Current Practices, Challenges and Impact C.P. Ravikumar and V.R. Devanathan (Texas Instruments) |
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| Tutorial – T4 | (Part 1) |
| Telemedicine Poornima Mohanachandran (i2iTeleSolutions) |
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| (Part 2) | |
| Assistive Devices for the Visually Impaired M Balakrishnan (IIT Delhi) |
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Tutorial – T1 (Participants restricted to 20)
(Venue: Cranes Software Intl Ltd, # 5, Airport Road, Domlur Layout, Bangalore – 560 071)
Open Source Embedded System Development using Beagleboard
Syed Khasim
(Texas Instruments India)
With the availability of low-cost platforms, open-source development of embedded systems is becoming possible for individual hobby-professionals and start-ups. In this tutorial, we will introduce the participants to the exciting world of open-source development using the Beagleboard as an example. Beagleboard is intended for low-power, high-performance embedded systems development and supports Linux operating system. A growing world-wide community of Beagleboard users collaborate on solving problems and come up with innovative solutions. In this tutorial, we will cover the following topics and provide some hands-on training on the Beagleboard.
The topics we will cover include:
· Introduction to Open Platforms
· Quick overview of the Beagle Board
· Open Software development tools
· Collaboration tools
· Validating beagle board peripherals with Linux tools on Beagle Board
· Introduction to Open Embedded
· Programming the DSP and ARM cores made easy
· Hands-on Training
About the speaker: Syed
Mohammed Khasim
started his career back in 2001 with Linux devices for Single board computers
and TI DSP applications & solutions. In 2004 he joined Texas Instruments as a
Linux Consultant through Wipro technologies. After spending last three years
(2004 - 07) in TI head quarters (Dallas, Texas USA) as a Linux Consultant and
Open Source Facilitator for Wireless software development & strategies, he moved
back to India and joined as a Technical Lead for Open Platforms in DSPS /
Catalog applications division of TI. In last couple of years, Khasim has
pioneered and lead various initiatives in TI to meet the increase in demand for
Mobile Linux on TI chipsets and processors. Khasim earned a bachelor’s degree in
Computer Science & Engg in 2001 from BMS college of Engineering, Bangalore,
India.
Tutorials T2, T3 & T4: (Venue: Learning Centre, Wipro Campus, Electronics City, Hosur Road, Bangalore)
Tutorial – T2
Compact Modeling and PDK’s
Madabusi Govindarajan,
Tamilmani Ethirajan, Abhisek Dixit, and Josef Watts (IBM)
This tutorial covers compact models and their roles and dependencies in a Process Design Kit (PDK). The emphasis throughout will be to understand the circuit consequences of compact models from an intuitive standpoint. We begin by dissecting a PDK and delve into the mutual dependencies of device views, modelcards, layout-versus-schematic (LVS) decks, and parasitic extraction (PEX) decks. We then pick up a “simple” device such as a poly resistor and demonstrate how harmonics and self-heating pose modeling challenges for RF front-end designs. Thereafter we escalate the device and model complexity to cover a variety of active and passive device models, culiminating in PSP models for ultra deep submicron FET’s. The roles of as-fit and centered models are analyzed in detail. Special emphasis is placed on FET A.C/Noise models and extraction, including the important role of the layout parametric cell-PEX boundary. Statistical modeling is also covered in detail, including Monte Carlo, fixed/functional corners, and statistical timing analysis.
About the speaker: Madabusi Govindarajan received his Bachelor's degree in Electrical Engineering from IIT-Madras in 1988, and the Ph.D degree also in Electrical Engineering from the University of Southern California, Los Angeles, in 1994. At USC he worked on high-speed circuits based on GaAs and InP HBT technologies. From 1994-99 he was a faculty member at the Department of Electrical Engineering, IIT-Bombay, where he became an Associate Professor. At IIT-B Govindarajan taught courses in analog circuits and electromagnetism, and pursued research projects in high-speed systems. From 1999-2002 he worked in the San Francisco Bay Area at LuxN, an innovative start-up in the metropolitan optical networking area. From 2002-05 he was with Scintera, a fabless Bay Area start-up that developed a path-breaking line of 10 Gbps electronic dispersion compensation IC's in standard CMOS. From 2005-2007 Govindarajan was with Signalguru, a Bangalore-based consultancy in high-speed test & measurement. In 2007 he joined IBM's Semiconductor R&D Center (SRDC) in Bangalore, where he is with the design enablement group, focusing on compact modeling of RF derivative processes. Govindarajan's technical interests are in high-speed/RF devices and circuits.
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| Madabusi Govindarajan | Tamilmani Ethirajan | Abhisek Dixit | Josef Watts |
Tutorial –
T3
Part-I
Test Cost Reduction Techniques, Current Practices, Challenges and Impact
Sarveswara
Tammali (Texas Instruments)
Test cost is becoming increasingly significant percentage of COB (Cost of Build) in current SoCs (System-on-a-Chip), accentuated by the need of more testing required in shrinking technology nodes. This is even critical in low cost markets like consumer devices. Test quality, which is measured in defective parts per million (DPPM) is becoming aggressive in growing competitive market. So, it is often delicate trade-off that is required to plan test cost strategy given test quality requirements and vice-versa. Strategy includes DFT architecture, target ATE and multi-site configuration and test flow strategy. There are well known DFT techniques namely parallel test, scan compression, built-in-self-test (BIST), which are key techniques in the low cost strategy. Current practices of multi-site test, concurrent tests, scan compression and BIST are discussed. Challenges and impact of these techniques are discussed in detail in this tutorial.
The tutorial also talks about some miscellaneous test cost reduction techniques that involve reduction of IDDQ stops and scan pattern optimization. Another important strategy for test cost reduction approach is to use low cost ATE (Automated Test Equipment) as a target tester for SoC. Some of common limitations of low cost ATE are frequency of interaction with DUT, accuracy of stimuli application and output strobe and limited number of tester resources. DFT and test pin muxing, timing closure needs to comprehend limitations of low cost ATE right from design start to be able to successfully utilize low cost ATE for most of tests if not all of manufacturing tests. Key challenges for product engineering team from multi-site point of view are power supply grouping, site-to-site variation, power supply noise and external components on board. In the last section, test cost reduction strategy is discussed which includes test time estimation and identifying critical test modes where test time reduction helps to reduce overall test cost are discussed.
About the speaker: Sarveswara Tammali, IEEE member, obtained an M.Tech in VLSI Design Tools and Technology from IIT Delhi (2001) and joined Texas Instruments India, where he has been responsible for DFT architecture, implementation and support for ramp for several multi-million System-on-a-Chip designs. He has presented several papers in both internal and external international conferences on topics related to Scan Compression, Test Cost Reduction and Failure Analysis. Currently he is actively involved in Test Cost Reduction process. He is also DFT lead for the SOC that has achieved lowest test cost (% of COB) at Texas Instruments and has won best RTP’ed device award with lowest test cost. He has earned his bachelor’s degree in ECE from JNTU College of Engineering, Anantapur, Andhra Pradesh.
Part-II
Test Power Reduction Techniques, Current Practices, Challenges and Impact
C.P. Ravikumar
and V.R. Devanathan
(Texas Instruments)
In this part of the tutorial, the speakers will focus on test power reduction. Test power is important from the viewpoint of preventing packaging decisions, device reliability and test effectiveness. The speakers will cover some of the recent techniques for test power reduction, such as hierarchical techniques for power reduction, glitch power reduction, and low-voltage scan shift technique.
About the speaker: C.P.
Ravikumar is a
senior technologist at TI India. He is also the secretary of the VLSI Society of
India since 2003. More details about him can be found at
http://cpravikumar.tripod.com
About the speaker: V.R. Devanathan obtained his B.E. from GCT, Coimbatore, M.Tech. (Computer Science) from IIT Madras, and Ph.D. (Computer Science) from IIT Madras. He has more than six years of industry experience. He is presently with Texas Instruments working on Design for Test related problems for the past five years. He has published papers in the area of Low-Power Testing in leading IEEE conferences and journals. His Ph.D. thesis won the best thesis award at the IEEE VLSI Test Symposium, 2008.
Tutorial – T4
Part-I
Telemedicine
Poornima Mohanachandran i2iTeleSolutions
This tutorial will begin by addressing the question of how the medical profession can benefit from technology, in particular, VLSI technology. The tutorial will provide a perspective on the new developments in the area of Tele-Medicine. The tutorial will bring out research & development opportunities and challenges for Indian academia and industry. As an illustration, the topic of medical image compression will be considered and a demonstration will be given of the software developed by an Indian R&D house.
About the speaker: Poornima Mohanachandran has held many executive level management responsibilities at Texas Instruments. She was GM of product development for high performance data converters at Texas Instruments and most recently Director of Business Development for Medical Business at TI. Here she was working with TI customers and medical industry on new opportunities for semiconductor devices in Medical Applications. She has 20 years of industry experience covering all aspects of product development and business development. Presently she is with i2iTeleSolutions a company focused on telemedicine solutions. At i2i she is responsible for strategy and development of telemedicine solutions.
Part-II
Assistive Devices for the Visually Impaired
M
Balakrishnan * (IIT Delhi)
In the last three years, an inter-disciplinary group working in the area of embedded systems has been formed at IIT Delhi. The focus of the group has primarily been to design innovative devices for assisting visually impaired persons. In this period we have now worked on four projects that are listed below.
1. Smart Cane
2. Bus identification system
3. Braille tutor
4. Disha: Indoor navigation system
The projects have reached various stages of completion including prototyping and have resulted in one technology transfer done to a company and the second ready for technology transfer. The tutorial would focus on two aspects:
§ Technical details and achievements of the four projects and
§ A successful model for involving undergraduate students in embedded systems design activity
The tutorial would be accompanied by demonstration of prototypes of these projects.
Visit for details - http://embedded.cse.iitd.ac.in/assistech
About the speaker: M
Balakrishnan is a
professor in the Computer Science Department, IIT Delhi. His research areas
include Embedded Systems, CAD for VLSI and Computer Architecture.