12th IEEE VLSI Design And Test Symposium
Advance Technical program
Program
Full-day Tutorials
6 hours
RFIC Design and Testing for Wireless Communications
Speakers: Vishwani Agrawal and Foster Dai, (Auburn University)
Abstract: Tutorial discusses design and testing of RF integrated circuits (RFIC). It is suitable for engineers who plan work on RFIC but did not have training in that area, those who work on IC design and wish to sharpen their understanding of modern RFIC design and test methods, and engineering managers. It is an abbreviated version of a one-semester university course. Specific topics include semiconductor technologies for RF circuits used in a wireless communications system; basic characteristics of RF devices – linearity, noise figure, gain; RF front-end design – LNA, mixer; frequency synthesizer design – phase locked loop (PLL), voltage controlled oscillator (VCO); concepts of analog, mixed signal and RF testing and built-in self-test; distortion – theory, measurements, test; noise – theory, measurements, test; RFIC SOCs and their testing.
Vishwani
D. Agrawal
is the James J. Danaher Professor of electrical and computer engineering at Auburn University. He has over 30 years of industry and university experience in VLSI design and test. He has authored five books, over 300 papers, and 13 patents. He holds a PhD from the University of Illinois at Urbana-Champaign.
For details, see www.eng.auburn.edu/~vagrawal
Foster Dai is a Professor of electrical and computer engineering at Auburn University. He designed many RFIC chips at several companies before becoming a professor. He holds PhD degrees from Pennsylvania State University and Auburn University. He has authored a book and numerous papers and patents in the area of RFIC design and test. For details, see www.eng.auburn.edu/users/daifa01
Part 1 - 4 hours
SoC Power Management Architecture Design and Verification
Speakers: Dr. Bhanu Kapoor (Mimasic), Shankar Hemmady (Synopsys), and Sandeep Aggarwal (TI)
Abstract: We are at the crossroads of some fundamental changes that are taking place in the semiconductor industry. Power consumption has become one of the most important differentiating factors for semiconductor products due to a major shift in the market towards handheld consumer devices. Power is a primary design criterion for bulk of the semiconductor designs now. Power is a key reason behind the shift towards multi-core designs as increase in power consumption limits increases in clock speed at the rate we have seen in the past.
Voltage is the strongest handle for managing chip power consumption. Dynamic power is proportional to the square of supply voltage and leakage power has a linear relationship with it. In addition, leakage power has an exponential relationship with the threshold voltage of the device. This implies that if voltage can be controlled to optimally meet the performance then there can be much to be gained in terms of power savings.
This tutorial focuses on introducing fundamentals of the SoC power management design and verification to the attendees. We look in detail at some of key power management techniques that leverage voltage as a handle: Power Gating (PG), Power Gating with Retention (RPG), Multiple Supply Voltages (MSV), Dynamic Voltage Scaling (DVS), Adaptive Voltage Scaling (AVS), Multi-Threshold CMOS (MTCMOS), and Active Body Bias (ABB).
The use of above mentioned techniques imply certain power management architecture design and partitioning of design in terms of voltage islands that are controlled through power management signals. We look at the challenges in power management architecture design utilizing some examples that incorporate state-of-the-art power management techniques.
The use of above mentioned techniques also imply new challenges in validation of designs as new power states are created. We look into the characteristics of typical power states that exist in such designs and detail the techniques used in design validation. Techniques that leverage simulation, formal, and rule-based techniques are described in detail using examples. We make use of industrial design examples to aid explanation of these points.
Bhanu Kapoor is a consultant and owner at Mimasic, a consulting services company in the area of low power chip design and verification. He has played leading technology development roles at EDA startups ArchPro (now Synopsys), Atrenta, and Verisity (now Cadence). He started his career with Texas Instruments where he played various technical roles (1987-99) at TI's R&D labs. He has helped set-up university technical advisory boards and played leading roles in joint industry and university research. Bhanu graduated from IIT Kanpur in 1987 with a degree in Electrical Engineering. He has received M.S. (1990) and Ph.D. (1994) degrees in Computer Science from SMU, Dallas. He is also an Adjunct Professor of Computer Science at SMU and serving as the Vice President of IIT Kanpur Alumni Association. He has authored over 30 IEEE/ACM conference/journal papers and has been granted 5 US patents in the area of low power design.
Shankar Hemmady is a Principal Engineer at Synopsys. He is responsible for verification solutions including planning, management, methodology and power-aware verification. Mr. Hemmady has designed, verified and tested, or managed the functional closure of over 25 commercial chips during the past 17 years of his tenure in the industry as an engineer, manager and consultant at 12 companies including AMD, Cirrus Logic, Fujitsu, Hewlett Packard, Intel, S3, Sun and Xerox. He has authored over 10 research papers and 10 articles in trade publications, and co-authored a book published by Springer, "Metric Driven Design Verification: An Engineer's and Executive's Guide to First Pass Success" in May 2007. Mr. Hemmady holds a B.S. in Electrical Engineering from the Indian Institute of Technology and an M.S. in Electrical & Computer Engineering from the University of Iowa. He completed Stanford's Advanced Management College executive program.
Sandeep Aggarwal manages the development of next generation OMAP SOC in Texas Instruments India. He has over 11 years of experience in different aspects of SOC design. His main expertise is in SOC clock control and power management with hands on experience on all generations of TI OMAP technology. Sandeep Aggarwal received his B.E. Honors (EE, CRSCE Haryana), M.Tech (Micro Electronics, IITB Mumbai) in 1995 and 1997 respectively. Sandeep has several publications in the field of clocking in complex SOCs and Power Management design/verification.
Ultra Low-Power Processors for Embedded Systems
Speaker: Atul Lele (Texas Instruments) and Gurjit Singh (Gill Instruments)
Abstract: Providing electrical power to operate an embedded system can be a challenge, since the system may be a portable or an implanted device and has to rely on batteries or harvested energy. With the growth of mobile internet devices which support a rich set of media applications, conserving mission-mode power requires careful consideration so as to avoid frequent recharging of batteries. In implanted devices, it may be virtually impossible to change or recharge batteries. As examples, consider a camera that can be implanted into the eye of a blind/partially blind person, or a wireless sensor network node that can be implanted in a locket that is placed on a wild animal for tracking its movements. Architectural breakthroughs are required to reduce the power dissipation of the processor to picowatts and still be able to provide adequate processing speed. In this tutorial, we will discuss the principles of operation of an ultra low-power processor which is popularly used in several embedded applications. We will also provide an overview of several emerging applications such as biomedical engineering where such processors are used.
Atul Lele completed his Bachelor of Engineering from Pune Institute of Computer Technology (PICT) in 2000. He is currently working as a Project Leader with MSP430 design group. He has been working on MSP430 for past 4 years and prior to that he that worked on C2000 based digital signal controllers. He has got expertise across different domains in the Chip Design Flow. E.g. Front-end verification, Silicon validation, RTL design, Synthesis and STA, Layout, Power estimation, Analog and Mixed signal simulations etc. He has done a few paper presentations at internal and external conferences.He is very passionate about being part of MSP430 design team. This is especially looking at different applications spaces where MSP430 can be a clear advantage over its counterparts and significant benefits MSP430 offers in terms of power, performance and cost.
Gurjit Singh Gill is the Director /Design Head, at Gill Instruments Bangalore, a third-party company of Texas Instruments. He has 7 years of work experience in the field of embedded systems. He holds a Bachelor's degree in Electronics & Telecommunication from J.N.E.C, Aurangabad. His has worked as an Embedded Design Engineer for G.E Power controls Bangalore, and also at Bajaj Auto, Garware Polyester, and Cosmo films; Everest Kento Cylinders, Vatan Textile, and Jacob Muller (India) Pvt. Ltd.
He presented a keynote speech, Embedded system design using MSP430 and conducted tutorials on Single chip Filter, at the Texas Instruments Developer conference during 2004-2005. He has worked on wireless Acoustic sensors using MSP430 for Fire Alarm system, implementing Filter algorithm and echo cancellation techniques. He has designed one of the first development tools to support Acoustic sensor interface that employed the on board microphone and low power amplifier with wire/wireless interface. Currently he is working on TCP/ IP, USB and wireless protocols.
Part 1 - 1.5 hours
Holistic Verification: Myth or The Magic Bullet?
Speaker: Pradip Thaker, Analog Devices
Abstract: With advances in submicron technologies over last decade, multi-million gate ICs have become a cliché. With growth in size of the design, the diversity in functionality on a single-chip has proportionally grown while the time-to-market pressures have remained unchanged. On a single-die, it is common to have variety of combinations of newly developed digital as well as mixed-signal/analog circuits, integration of in-house and/or 3rd party IPs, integration of mega-blocks such as RAMs and ROMs, single or multiple instances of processor core(s), implementation of newly developed algorithms or standards with strict requirement for logical and electrical compliance, variety of standard and non-standard interfaces, integration of building blocks created through orthogonal design flows such as RTL and custom design. With convergence of these multiple disciplines on a single-die, verification of such IC is beyond the scope of any single verification approach. Even brute-force cumulative deployment of all verification techniques each of which is traditionally used to tackle a respective challenge is insufficient to produce high-quality robust first silicon. In this presentation, a holistic verification strategy will be defined and discussed with aim to provide guidelines for high-confidence verification sign-off of high-end multi-million gate devices with feature and flow diversities. Trade-offs of various emerging and incumbent verification techniques will be presented along with best practices from both, academics and industry.
Dr. Pradip Thaker has 15 years of industry experience combined both as a technical manager and individual contributor in developing large and complex ICs for networking, multi-media and computer connectivity with semiconductor and system companies in USA and India. He also served as an adjunct faculty at the George Washington University (Washington DC, USA) from years 1993-2003 where he designed and taught undergraduate and graduate level VLSI courses on part-time basis. He received BE (ECE), MS (EE) and PhD (VLSI Systems) in 1989, 1993 and 2000 respectively.
He is currently with DSP IC Division of Analog Devices, Inc. in Bangalore, India.
Dr. Pradip Thaker is recipient of industry and academic awards for excellence. He has published in international conferences and regularly reviews papers for the same. His technical contributions in industry are in the areas of architecture definition, RTL implementation, verification, synthesis and DFT. His academic research interests are in area of DFT and verification.
Foundations of Design Verification- Formal and Functional Approaches
Speakers: Ansuman Banerjee; Kausik Datta; and Amit Roy (Interra Systems India Pvt. Ltd.)
Abstract: Design verification is the process of ensuring that a design meets its specifications. This tutorial introduces the concept of hardware design verification, and briefly covers the different methods of design verification and their respective strengths and weaknesses. On one hand, in this discussion, we intend to provide an in-depth understanding of formal verification with discussion on symbolic and SAT-based approaches along with a comprehensive overview of the basic building blocks of a formal verification tool. On the other hand, we discuss in detail the established principle of simulation-based functional validation along with state-of-the art developments in this area. In the concluding part of the discussion, we mention two advanced issues of interest in the verification community today. The tutorial will also involve brief demos of some verification tools available in the public domain.
Session-1 (a): Introduction to Design Verification: * Introduction to the design validation problem * An overview of existing technologies and design verification challenges Session-1 (b): A comprehensive overview of Formal Verification: * The concept of Model Checking * Binary Decision Diagrams and Symbolic Model Checking * SAT-based Bounded Model Checking * Overview of tools from the academia and industry Session-2 (a) : Functional Verification: * Test-bench design and Transactor based modeling * An overview of modeling support in System Verilog * Standard Methodologies in Test-bench Design Session-2 (b): Advanced Issues: * Consistency Issues in Assertion-based verification * Coverage Issues in Formal and Functional Verification
Ansuman Banerjee is presently working as
a Principal Engineer in the verification group at Interra Systems. He has
completed his post-graduate and doctoral dissertations in the area of formal
and semi-formal verification from the Indian Institute of Technology,
Kharagpur. He has about 20 publications in areas related to verification in
national and international conferences (DAC, ICCAD, VLSI etc.) and journals
(ACM TODAES, IEEE TCAD etc). He has served on the Technical Program
Committee of DVCON 2008 and has been a reviewer of the international
conference on VLSI Design and VLSI Design and Test Symposium (VDAT).
Design Verification using Static Checker and Verification of Clock-domain Crossing
Speaker: Kaushik De, Synopsys
Abstract: As design complexities are growing, design verification problem is exploding. Simulation remains the main vehicle for design verification. However, design complexities make it extremely difficult to cover all cases of the design. Formal verification are used to prove properties of the design, however the capacity of the tool remains an obstacle. In addition, Formal verification technology usage requires deep expertise. Static Checker technology offers another very good alternative, which can identify potential issues in the design by doing static analysis of the design. For example, it can identify if the design can have simulation synthesis mismatch or potential race condition during simulation, or operand type or width mismatch, unintentional latch in the design, etc. In addition, it can detect many fundamental issues such as clock/reset/connectivity, etc. It can also detect correctness in signal connectivity in multi-power domain designs. Hence, deployment of static checker technology will greatly enhance the design verification capability.
The modern designs have many clock domains, and special care need to be taken in designing the part where signal traverses from one clock domain to another. Designing and verifying interaction between signals between asynchronous clock domains is major challenge, because signals crossing clock domains need to follow strict rules to ensure correct functionality. Many design re-spin happens due to bug in clock-domain crossing issues. In order to verify correctness of clock-domain crossing, comprehensive methodology needs to be followed encompassing structural, formal and simulation techniques.
Kaushik De received B. Tech from IIT Kharagpur, and MS and PhD from University of Illinois at Urbana-Champaign. He worked in various technical & management roles in LSI Logic, Ambit, Cadence, Synopsys, and various startup companies, in US and India. He has worked in the area of Synthesis, DFT, and Design Verification. Currently he is R&D Director at Synopsys, working in Design Verification area, driving the static checker technology. He has published more than 25 technical papers at conferences and journals, and holds 5 US patents, 1 pending.
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