VSI
10th IEEE VLSI Design And Test Symposium
VDAT2006
August 9 - 12, 2006   International Centre, Dona Paula, Goa
Advance program

VDAT2006
Venue
Travel Details
Hotels at Goa
Guideline to authors

Brochure
Information Flyer
Registration Form
Fellowship Form
Accepted Papers
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VLSI Design And Test Symposium  2006
To promote applications and research related to all aspects of VLSI in India
VDAT

At a Glance...

Call For Participation

The 10th VLSI Design and Test Symposium (VDAT 2006) will be held at International Centre, Goa; during August 9-12, 2006.  To download the information flyer, please click on the link below:


Contact

For registration, fellowship and other general VDAT2006 queries, contact us.
Corporate sponsors and exhibitors must contact the General Chair for details of sponsorship.

Registration

Symposium
Registration Amount
Before June 30, 2006
After June 30, 2006
Fellow
Rs.1500/=
N/A
Indian Faculty/ Student
Rs.2500/=
Rs.3000/=

Indian Industry VSI/ IEEE Member

Rs.6000/=
Rs.7000/=
All Foreign Participants
US$ 150.00
US$ 200.00
Others
Rs.7000/=
Rs.8000/=

Tutorial
Registration Amount
Before June 30, 2006
After June 30, 2006
Fellow
Rs.1000/=
Rs.1500/=
Indian Faculty/ Student
Rs.1500/=
Rs.2000/=

Indian Industry VSI/ IEEE Member

Rs.2000/=
Rs.2500/=
All Foreign Participants
US$ 100.00
US$ 125.00
Others
Rs.2500/=
Rs.3000/=

Tutorials

Three parallel tutorials T1, T2, and T3 will be run on Day-1 9 August 2006.
Tutorial I    Analog Design
Tutorial II   Low Power Electronics and Future Technologies
Tutorial III Testing and Verification

Participants may register for any one of the following tutorials. Tutorial registration is separate from Symposium registration. They must indicate the choice of tutorial T1, T2, or T3 at the rear side of DD. Please send separate regisitrations for Tutorial and Symposium.

Tutorial - I: Analog Design
Analog design in monolithic IC confronts seemingly insurmountable problems due to poor tolerance components and temperature and supply dependant parameters. Further, passive components take up considerable area. The tutorial explains strategies to tackle these problems. These techniques can also be adopted in digital designs for improving yield and reducing power dissipation. The tutorial will be given by two experts in the area (a) Prof.KRK Rao, who is currently with Texas Instruments India and was a Professor at IIT Madras before he joined TI India, and (b) Prof. Dinesh Sharma, a Professor in the Department of Electrical Engineering at IIT Bombay.

Tutorial II: Low Power Electronics and Future Technologies
Power dissipation is a major concern in modern VLSI circuits. The first part of the tutorial, which will be taught by Prof. Vishwani Agrawal of Auburn University, will deal with methods to reduce power dissipation at various levels of abstraction system-level to gate-level. The second part of the tutorial, which will be taught by Prof. D. Mukhopadhyay and Dr P.K. Basu of Jadavpur University, will consider future technologies that are likely to follow the CMOS technology. The main challenge of nanoelectronics is to exploit quantum behavior and to solve the problems we face: inherent uncertainties and inaccuracies, interconnection problems and the enormous design complexity. Nanoelectronic technology requires an unconventional approach. Although the technology is still in its infancy, time is ripe now to investigate the opportunities for circuits and systems. The tutorial introduces some of the phenomena in nanoelectronics, discuss the device behaviors and to highlight the opportunities that get opened up in the area of integrated circuits and systems. The third part of the tutorial, taught by C. Venkatesh of Indian Institute of Science, will consider the implementation of capacitors in VLSI with emphasis on MEMS capacitors. Design, analysis, characterization methods and applications will be covered in detail. The theory required for Analysis of Capacitors, Low-frequency Analysis and Applications and High-frequency Analysis and its Applications would be dealt.

Tutorial III: Testing and verification
This tutorial consists of two parts. In Part I, which will be delivered by Baijayanta Ray, Venkataraghavan PK, and Sriram Balasubramanian from Synopsys, India, the presenters describe a reliable verification methodology, which ensures low risk while going for first time silicon. This methodology has been successfully applied in developing baseband subsystems for various wireless systems such as GSM, W-CDMA, DAB, MBOA-UWB, and proprietary systems for satellite & terrestrial communication applications. The second part of the tutorial, which will be delivered by Prof. Indranil Sengupta of IIT Kharagpur, covers the testability issues involved in the design of core based systems. Standardization efforts in this regard will be discussed, with special emphasis on IEEE 1500 standard for embedded core test, CTL, etc.

After completing the Registration form, please mail it with draft made out to:
VDAT Symposium 2006 payable at Bangalore to:

Mr. Gopal Naidu
Finance Chair, VDAT2006
VLSI Society of India,
c/o ARM Embedded Technologies Pvt Ltd.
Bagmane World Technology Center - SEZ
Citrine Block, 5th Floor
Marathahalli Outer Ring Road,
Doddanakundi Village,
Mahadevapura,
Bangalore - 560 048

Important Dates

  • Last Date for Paper Submission: March 15, 2006
  • Last Date for Tutorial Submission: March 31, 2006
  • Notification of Acceptance: May 1, 2006
  • Last Date for Sending Final Manuscript: June 1, 2006
  • Last Date for Fellowship Application: May 15, 2006
  • Full-day Tutorials: August 09, 2006
  • VLSI Education Day: August 10, 2006
  • Symposium Dates: August 09-12, 2006

Technical Tracks

VDAT symposium runs in three concurrent technical tracks:

  1. Track on High-level Design will discuss issues related to system-level synthesis, microarchitecture, embedded systems, codesign, core-based design of SoC, timing convergence, high-level synthesis, logic synthesis, memory synthesis, and FPGA synthesis.

  2. Track on Physical Design and VLSI Technology will discuss all issues related to physical design and process related aspects of integrated circuits, such as layout, fabrication, packaging, opto-electronic circuits, MEMS, deep submicron and nanometer devices.

  3. Track on Testing and Verification will discuss issues related to testing, testability, and verification of digital designs, memories, analog designs, and mixed-signal designs, and circuits containing deep-submicron and nanometer devices.

Technical Paper Presentations

The last date for Paper Submission has now passed.  If you have submitted a paper, you will shortly hear about our decision about the paper-review and selection!

Tutorials & Panel Discussions

Details of tutorials will become available by June 2006. Three parallel tutorials T1, T2, and T3 will be run.

If you have submitted proposals for embedded tutorials (1 hour or 2 hour duration), full-day and half-day tutorials, you will shortly hear from us about our decision. 

We invite proposals for panel discussions.    The proposal must include an extended abstract, the agenda and profiles of the speakers.

Get Involved!

We invite your ideas and suggestions for making VDAT 2006 symposium a memorable experience to all.  It could be setting up of University Booths or putting up of Industrial Exhibits.  There could be proposals for best paper awards, proposals for panel discussions, proposals for design contests, or even proposals for sponsorships! Participants can contribute their ideas, for making the Symposium an enriching experience for all.  Please express your ideas to us!

Corporate sponsors and exhibitors must contact the General Chairs for details of sponsorship.

VDAT2006 Details
Accepted Papers
Advance Program
GIC Accommodation
Fellowship
Student Accommodation
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