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VLSI Design And Test Symposium  2006
To promote applications and research related to all aspects of VLSI in India
VDAT

VLSI Design And Test Symposium 2006 August 9-12, 2006 Goa, India

Decisions of the Program Committee

The list of papers selected for VDAT2006 Symposium

Accepted Papers marked were not presented at the Symposium

Paper

Title

Category

103

A Novel Distributed and Interleaved FIFO for Source-synchronous Interconnect
Santosh Sood, TI India, Mark Greenstreet and Resve Saleh, University of British Columbia, Canada

Regular Paper

107

Handling Trapezoidal Conductor Cross-sections in a Statistical Capacitance Extractor
Subramanian Rajagopalan and Shabbir Batterywala, Synopsys India

Regular Paper

124

Implementation of MPEG4 Video Decoder on a SoC Multimedia Processor
Prashanth P, Raghuveer P S, Celstream Technologies, Bangalore, Vinayak A.S. and C.R.Venugopal, SJCE, Mysore

Short Paper

128

Highly Linear, Highly Efficient Power Amplifier Design Using Diode Nonlinear Capacitance
Mrunal. A.K., IITB , Makarand Shirasgaonkar, Qualcore Logic Ltd, Hyderabad and Rajendra Patrikar, VNIT, Nagpur

Short Paper

137

Novel Architecture of Context Modeling for JPEG2000 & a comparison with Taubman's Architecture
Pratyush Aditya Kothamasu, Anand Gautam, A. Geeta Madhuri and Priya Khandelwal, DA-IICT

Regular Paper

145

Low Voltage Sample and Hold circuit
Vimitha Kuruvilla, CET

Short Paper

158

Automatic Test Generation for Temporal Coverage Points Using a Stochastic Tree Model
Anindyasundar Nandi, Bhaskar Pal, Pallab Dasgupta and Partha P. Chakrabarti, IIT Kharagpur

Regular Paper

159

Efficient DRC for Verification of Large VLSI Layouts
Prosenjit Gupta and P.K. Ganesh, IIIT

Short Paper

172

RF Energy Scavenging for Wireless Sensor Nodes
Shantanu Bhalerao, Abhishek Chaudhary, Raghavendra Deshmukh and Rajendra Patrikar, VNIT Nagpur

Regular Paper

183

A Dedicated Processor to Realize Inverse Radon Transform for CT Imaging
Abhishek Mitra and Swapna Banerjee, IIT Kharagpur

Short Paper

186

High Performance and Area Efficient n-BIT Tree Based Binary Squarer
Gopal Paul and Samir Satpathy, IIT Kharagpur

Regular Paper

196

Energy Efficient Application Specific Banked Register Files
Rakesh Nalluri and Preeti Ranjan Panda, IIT Delhi

Regular Paper

216

Detecting Faults at the Time They Occur
Abhijeet Kumar, Sayantan Das, Pallab Dasgupta and P. P. Chakrabarti, IIT Khargpur

Regular Paper

219

Constructing Online Testable Circuits Using Reversible Logic
Noor Mahammad, Siva Kumar Sastry, Shyam Shroff and V. Kamakoti, IIT Madras

Regular Paper

233

Detection of Bridging Fault in Reversible Circuits
Hafizur Rahaman, Dipak K. Kole, Bengal Engg. & Science University, Debesh K. Das, Jadavpur University and Bhargab B. Bhattacharya, ISI Kolkata

Regular Paper

235

SOC implementation of the neural network based isolated word recognition
V. Amudha, B.Venkataramani, J.Karthick and C.Praveen, N.I.T, Tiruchirapalli

Short Paper

242

Design of Hardware Coprocessor for OTDR Application
Ponnmozhi Sampangi and Nitin Chandrachoodan, IIT Madras

Regular Paper

245

An Energy-Efficient Packet Filtering Architecture for Wireless Sensor Nodes
Prashant Sonone and Saswat Chakrabarti, IIT Kharagpur

Short Paper

247

A Novel all Digital Phase Locked Loop for Phase Tracking in GPS Receivers
S Moorthi, K Pavithra, MIT Campus, Anna University and J Raja Paul Perinbam CEG, Anna University

Regular Paper

262

Design and Optimization of On-chip Spiral Inductor for Silicon Based RF IC'S
Genemala Haobijam and Roy Paily, IIT Guwahati

Short Paper

267

A Novel Unified Framework for Functional Verification of Processors Using Constraint Solvers
Debi Prasad, Archna Rai, Karthik. V, Senthil Kumar, V. Kamakoti, Kailasnath S and Vivekanada Vedula

Short Paper

284

Study and Charecterization of Gallium Arsenide (GaAs) and Indium Phosphide (InP) Devices for Nanoapplications
E.N.Ganesh, P.K.Singh, BSA Crescent Engg college, Chennai and Lal Kishore, JNTU Hyderabad

Short Paper

322

A Novel CMOS Compatible Three Terminal 3D Tunable Micro Inductor
V. Siva Rama Krishna, K.Jayant and Navakanta Bhat, IISc Bangalore

Regular Paper

324

Design and Power-Performance Optimization of A Low Leakage Serial CAM
N. N. Mojumder, A. Dandapat and D. Mukhopadhyay, Jadavpur University

Regular Paper

325

Gas Sensor Interface ASIC on 0.7m CMOS Technology
Shobi Bagga, Navakanta Bhat and S.Mohan, IISc Bangalore

Short Paper

326

General Purpose Capacitive Sensing Circuit using Correlated Double sampling
Sandeep K, Chaitanya K and Navakanta Bhat, IISc, Bangalore

Regular Paper

329

Critical Path modeling for Dynamic Voltage Scaling (DVS) in Low Power Applications
Bishnu Prasad Das, Bharadwaj Amrutur and H.S. Jamadagni, CEDT, IISc Bangalore

Regular Paper

333

Design & Study of an Electrostatic Torsion Micro Actuator for Beam Steering in Horizontal Plane
D. Vijaya Bhargava and Roy P. Paily, IIT Guwahati

Regular Paper

340

Fault Tolerant FPGA using Redundant Columns
Neeraj Goel and Kolin Paul, IIT Delhi

Short Paper

347

FPGA Implementation of a new hardware architecture for Smoothing Two Dimensional Images
Narasimhan Venkateswaran, SVCE, Sriperumbudur and Y.V Ramana Rao, College of Engg, Anna University

Short Paper

356

A Novel Low Power Bus Encoding Technique for Minimizing RGB Transitions for LCD Display of Digital Camera
J.V.R. Ravindra, K.S. Sainarayanan and M.B. Srinivas, IIIT, Hyderabad

Regular Paper

359

An efficient FPGA Implementation of a Cryptographic Hash Algorithm Based on Cellular Automata
Roshni Chatterjee and Dipanwita RoyChowdhury, IIT Kharagpur

Regular Paper

363

A Power-Efficient Architecture for the 2-D Discrete Wavelet Transform
Rahul Jain, CoWare India and Preeti Ranjan Panda, IIT Delhi

Short Paper

367

Design and Implementation of Morphological Operations and Median Filter for Image Processing Applications
Kapadia Payal Rohit, Nirma University, Ahmedabad, Raj Singh and Ravi Saini, CEERI

Short Paper

371

A Novel LO circuit for Sub-Harmonic Mixer
R.N.Biswas, Prof. C.Parikh, DA-IICT and G.P.Krishna Kishore, ATLAB Inc, Korea

Regular Paper

374

Exact Method for Estimating Expected Settling Power in Sequential Circuits
Diganchal Chakraborty, P.P.Chakrabarti and Pallab Dasgupta, IIT Kharagpur

Regular Paper

375

A Fully On-chip automatic gain control for RF-Transceivers complying IEEE 802.15.4, LR-WPAN
Harsh T, SIT Lonavala, Abhay N.A, BVP Pune and Tawade R, SCOE

Short Paper

379

Waveform Analysis and Delay Prediction for a CMOS Gate Driving RLC Interconnect Load
B.K.Kaushik, IIT Roorkee, S.Sarkar, Modi Inst. of Tech. & Sc., Sikar and R.P.Agarwal

Short Paper

384

Comparison of Compression techniques for FPGA configuration bit stream
Komala Soares, PCCE, Verna, Goa

Short Paper

387

Simulation Of Silicon Nanowire Field Effect Transistors, Carbon Nano Tube Field Effect Transistors and Comparison with Double Gate di-Electric silicon MOSFET
E.N.Ganesh, P.K.Singh, BSA Crescent Engg college, Chennai and Lal Kishore, JNTU Hyderabad

Short Paper

392

A Novel Algorithm for Fault Diagnosis in Analog Circuits using Small Change Sensitivity Computation
Vishal Gupta, ST Microelectronics, Subash Chandra Bose, CEERI and Dinesh Jain, Analog Devices

Short Paper

394

An Improved Direct Injection Readout Structure for IR FPA
G.Rajahari, Anil K.Saini, S.C.Bose and Chandra Shekhar, CEERI

Short Paper

405

Architectural Design and Implementation of a PC based Ultrasound Imaging System
Bodhisatwa Mazumdar , Aman Mediratta, Joydeep Bhattacharyya and Swapna Banerjee, IIT Kharagpur

Short Paper

406

Design of an Efficient Low Power AES Engine for Zigbee Systems
Ninad B Kothari, T.S.B. Sudarshan, Shipra Bhal, Tejesh.E.C, S. Gururnarayanan, BITS Pilani

Short Paper

407

On the Quality of Transition Fault Tests
Jais Abraham, InnoDes Solutions, Bangalore and Sandeep Jain, TI India

Regular Paper

412

Spectral Characterization of Functional Vectors for Gate-Level Fault Coverage Tests
Nitin Yogi and Vishwani Agrawal, Auburn University

Regular Paper

414

Cross talk Aware Multi-objective Optimal Routing for Island Style FPGA
Vineet Sahula, MIT Jaipur and Rajesh Tiwari, TI India

Short Paper

415

Electrostatic Discharge Reliability for designers

Tutorial

416

Silicon Technology Scaling and ESD Reliability

Tutorial

417

Compact modeling and simulation for ESD protection design

Tutorial

420

Robust Power Delivery for Sub-100nm Integrated Circuits
Thenappan Meyyappan, V Visvanathan, TI India and S.K.Nandy, IISc Bangalore

Embedded Tutorial

421

Beyond CMOS: Problems and Prospects of Nanoelectronics

Tutorial

423

MEMS capacitors

Tutorial

424

Design and Testing Issues in Core Based Systems

Tutorial

425

Integrated Stability Analysis Methods for Hybrid Systems
S. Jairam, Texas Instruments India and Navakanta Bhat, IISc Bangalore

Regular Paper

426

Design and Analysis of Robust Clock Trees
B.G.Madhusudan Rao, Jagdish Rao, Vish Viswanathan and Udayakumar H, TI India

Embedded Tutorial

427

System-level Verification of Wireless Systems

Tutorial

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